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Nitrided Hafnium Silicate Film Formation by Sequential Process Using a Hot Wall Batch System and Its Application to MOS Transistor

Published online by Cambridge University Press:  01 February 2011

Tomonori Aoyama ,
Kazuyoshi Torii ,
Riichirou Mitsuhashi ,
Takeshi Maeda ,
Satoshi Kamiyama ,
Atsushi Horiuchi ,
Hiroshi Kitajima  and
Tsunetoshi Arikado
Tomonori Aoyama
Affiliation:
Research Dept. 1, Semiconductor Leading Edge Technologies, Inc. 16–1 Onogawa, Tsukuba 305–8569, Japan
Kazuyoshi Torii
Affiliation:
Research Dept. 1, Semiconductor Leading Edge Technologies, Inc. 16–1 Onogawa, Tsukuba 305–8569, Japan
Riichirou Mitsuhashi
Affiliation:
Research Dept. 1, Semiconductor Leading Edge Technologies, Inc. 16–1 Onogawa, Tsukuba 305–8569, Japan
Takeshi Maeda
Affiliation:
Research Dept. 1, Semiconductor Leading Edge Technologies, Inc. 16–1 Onogawa, Tsukuba 305–8569, Japan
Satoshi Kamiyama
Affiliation:
Research Dept. 1, Semiconductor Leading Edge Technologies, Inc. 16–1 Onogawa, Tsukuba 305–8569, Japan
Atsushi Horiuchi
Affiliation:
Research Dept. 1, Semiconductor Leading Edge Technologies, Inc. 16–1 Onogawa, Tsukuba 305–8569, Japan
Hiroshi Kitajima
Affiliation:
Research Dept. 1, Semiconductor Leading Edge Technologies, Inc. 16–1 Onogawa, Tsukuba 305–8569, Japan
Tsunetoshi Arikado
Affiliation:
Research Dept. 1, Semiconductor Leading Edge Technologies, Inc. 16–1 Onogawa, Tsukuba 305–8569, Japan
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Abstract

High quality HfSiON/SiO2 gate dielectrics were successfully formed using a hot wall batch system, which is suitable for mass production. The carbon contamination at HfSiON/SiO2 interface was reduced by a sequential process of the interfacial layer (IL) formation and HfSiOx metal organic chemical vapor deposition (MOCVD). The O3 treatment was found effective to reduce the residual carbon and hydrogen, while the NH3 treatment made the HfSiOx to be HfSiON, which was effective to prevent the phase separation and crystallization during the activation annealing. The NH3 treatment temperature above 700°C is necessary to suppress the boron penetration during the activation annealing at 1050°C for 1 sec in p-channel field effect transistor (p-FET). Equivalent oxide thickness (EOT) of 1.37 nm was achieved for HfSiON· (3nm)/SiO2(0.5nm) gate stack using poly-Si electrode. High effective mobility of 271/62 cm2/Vs (n/p at 0.8 MV/cm) was obtained.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 786: Symposium E – Fundamentals of Novel Oxide/Semiconductor Interfaces , 2003 , E4.9
Copyright
Copyright © Materials Research Society 2004

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References

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