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A Multilayer Interconnect Process for 0.5um Logic Technology

  • Donghyun Kim (a1), H.S. Oh (a1), K.Y. Lee (a1), Y.S. Kim (a1), B.S. Kim (a1) and B.G. Kim (a1)...


A submicron triple metal process for 0.5um logic CMOS is described, focusing on key process steps such as the dielectric planarization and metallization. The main emphasis has been placed on development of ar complicated planarization process utilizing SOG (Spin on Glass) etchback. In this paper, we report process data of triple metal technology which uses aluminum alloy for interconnects and P-TEOS (Plasma Tetra Ethyl Ortho Silicate) with siloxane SOG and etchback process for planarization.



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