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Monitoring Iron Contamination in Silicon by Surface Photovoltage and Correlation to Gate Oxide Integrity

Published online by Cambridge University Press:  21 February 2011

Worth B. Henley ,
Lubek Jastrzebski  and
Nadim F. Haddad
Worth B. Henley
Affiliation:
Center for Microelectronics Research, University of South Florida
Lubek Jastrzebski
Affiliation:
Center for Microelectronics Research, University of South Florida
Nadim F. Haddad
Affiliation:
IBM Corporation, Manassas, VA
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Abstract

The effects of iron contamination on gate oxide characteristics are examined from an experimental and modeling perspective. Gate oxide integrity is measured for silicon wafers contaminated with 1010 to 1014cm−3 of iron. Thermal oxides of 8, 10,13 and 20nm are studied. Iron concentration in silicon is measured non-destructively using Surface Photovoltage (SPV) minority carrier lifetime analysis. The SPV analysis technique is described. Based on the experimental data, allowable threshold iron contamination levels for various gate oxide thicknesses are established. For 10nm oxides, iron concentration cannot exceed 8×1010cm−3 without severe degradation in oxide quality. The threshold contamination level for 20nm oxides is 200 times higher. Time dependent dielectric breakdown (TDDB) test results indicate detrimental reliability effects can occur at even lower contamination levels.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 315: Symposium Y – Surface Chemical Cleaning and Passivation for Semiconductor Processing , 1993 , 299
Copyright
Copyright © Materials Research Society 1993

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