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Issues and Challenges of Chemical Mechanical Polishing for Nano-scale Memory Manufacturing

  • Choon Kun Ryu (a1), Jonghan Shin (a2), Hyungsoon Park (a3), Nohjung Kwak (a4), Kwon Hong (a5) and Sungki Park (a6)...


As the design rule of memory devices is scaled down to nanoscale, the number of the CMP process has increased considerably due to the complexity of integration scheme. The CMP for isolation has increased significantly because the isolation process of metal contact plugs and damascene metallization at nanoscale has been successfully enabled by the CMP. The CMP selectivity, which depends strongly on the chemistry of the slurry, must be tuned for the various new materials. Recently, in order to get over the limitation in lateral shrinkage of the memory device, several emerging applications have been investigated extensively. A vertical integration needs the new CMP process such as high removal rate Cu CMP. Next generation memories need the CMP process for new materials such as GeSbTe, conductive oxide, and magnetic materials. Since any nano-size scratch will be a killer defect at the nanoscale memory, both the CMP equipment and the consumables must be maintained with tighter degree of control specifications.



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1 Steigerwald, J.M. et. al., IDEM, San Francisco, USA (2008)
2 Jung, W.Y. et. al., SPIE Advanced Lithography, San Jose, USA (2009)
3 Lai, S., IDEM, San Francisco, USA (2008)
4 Liu, Z. and et. al., ICPT Proceedings, Hsinchu, Taiwan (2008)
5 Chung, S.W. et. al., Symposium on VLSI Tech., Kyoto, Japan (2007)
6 Jeong, Moon-Ki, The 38th Korean CMP UGM, Ansan, Korea (2008)



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