The power of VLSI circuits is, to a large measure, derived through an extensive network of fine-line metalization interconnects used to wire up various components on the chip. For example, the 1Mb DRAM utilizes three levels of conductors to interconnect over one million each of transistors and capacitors on a chip. The combination of larger chip dimensions and finer scaling generates several technology concerns that must be addressed by a variety of measures, including an optimum choice of metalization processes. These concerns are related to parasitics, defect density and generic reliability.
This talk will review trends in materials/processes to control RC time constants, series resistances, fine-line metal defects during pattern transfer, control of topography-related defects and generic reliability related issues such as contact electromigration and ∝-particle sensitivities.