Several aspects of the integration of diffusion-less junctions in a NMOS and PMOS conventional flows are evaluated. Processes as Solid Phase Epitaxial Regrowth (SPER) or advanced annealing techniques, as flash or laser, demonstrates benefits not only on the 1D junction profiles but also on the transistor characteristics. An optimization of the implants and of the annealing conditions lead to improved or equivalent transistors performance and short channel effects control compared to the conventional spike RTA process. A significant gain in the overlap capacitance could allow for reduced CV/I. Furthermore the junction leakage can be lowered down to the values reached with the conventional spike RTA process.