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Integration of CMP Fixed Abrasive Polishing into the Manufacturing of Thick Film SOI Substrates

Published online by Cambridge University Press:  01 February 2011

Martin Kulawski ,
Hannu Luoto ,
Kimmo Henttinen ,
Tommi Suni ,
Frauke Weimar  and
Jari Mäkinen
Martin Kulawski
Affiliation:
VTT Microelectronics, Tietotie 3, P.O. Box 1208, FIN-02044 VTT; Espoo; Finland
Hannu Luoto
Affiliation:
VTT Microelectronics, Tietotie 3, P.O. Box 1208, FIN-02044 VTT; Espoo; Finland
Kimmo Henttinen
Affiliation:
VTT Microelectronics, Tietotie 3, P.O. Box 1208, FIN-02044 VTT; Espoo; Finland
Tommi Suni
Affiliation:
VTT Microelectronics, Tietotie 3, P.O. Box 1208, FIN-02044 VTT; Espoo; Finland
Frauke Weimar
Affiliation:
3 M Deutschland GmbH; Carl-Schurz-Str.1; D-41453 Neuss; Germany
Jari Mäkinen
Affiliation:
Okmetic Oy; Piitie 2; P.O. Box 44; FIN-01301 Vantaa; Finland Contact:martin.kulawski@vtt.fi
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Abstract

The specification for the total thickness variation (TTV) of the device layers on thick-film silicon on insulator (SOI) wafers tighten for future applications. Therefore, the bulk removal polishing process of current technology after grinding cannot meet the demands in terms of flatness. The currently required amount of material removal for polishing out the induced sub surface damage (SSD) of the grinding is very high. Additionally, slurry-based CMP processes show unsatisfactory grindline and topography removal. This in turn reflects negatively to processing times, throughput and overall flatness performance.

Encouraging early results of FA pad use for silicon and SOI polishing have already been further developed [1]. Low SSD grinding has been introduced to silicon manufacturing [[1]]. In this work, an integrated manufacturing process sequence is presented. Starting from low SSD grinding of the bonded SOI wafer couple, an optimized FA CMP step is replacing the conventional bulk polishing with reduced removal. The SSD after FA CMP is investigated by oxide induced stacking fault (OISF) method [[2]] and results are used to adjust the final polishing step of the substrates. The overall process sequence is highly advantageous in terms of performance in TTV and provides a highly competitive and effective method for achieving best possible surface quality with minimized total silicon removal. This method is not only useful for SOI wafers but also in other areas of silicon processing.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 867: Symposium W – Chemical-Mechanical Planarization-Integration, Technology and Reliability , 2005 , W3.4
Copyright
Copyright © Materials Research Society 2005

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References

[1]: Kulawski, et al. in Advances in the CMP Process on Fixed Abrasive Pads for the Polishing of SOI substrates with high Degree of Flatness, ed. by Boning, D. S., Bartha, J. W., Philipossion, A., Shinn, G., Vos, I., (Mater. Res. Soc. Proc. 816, Warrendale, PA, 2004) pp. 191–196 Google Scholar
[2]: ASTM, Standard F1727-02: Standard Practice for Detection of Oxidation Induced Defects in Polished Silicon Wafers, ASTM 2002 Google Scholar
[3]: Kulawski, et al. in A novel CMP Process on Fixed Abrasive Pads for Manufacturing of highly planar thick film SOI Substrates, ed. by Boning, D. S., Devrient, K., Oliver, M. R. Stein, D. J., Vos, I., (Mater. Res. Soc. Proc. 767, Warrendale, PA, 2003) pp. 133–139 Google Scholar
[4]: Haapalinna, A. et al. in Rotational grinding of silicon wafers- sub-surface damage inspection, Mat. Sc. & En. B107 (2004), 321–331 Google Scholar
[5]: Werkstoffe der Halbleitertechnik, ed. by Hadamovsky, H.F., Leipzig, Germany, 2003 Google Scholar