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Improved off-Characteristics of a-Si Vertical-Type Mosfets

  • Hiroyuki Okada (a1), Jun'ichi Sakano (a1), Shunri Oda (a1) and Masakiyo Matsumura (a1)

Abstract

We propose a new structure of vertical a-Si FET with the intermediate layer between the source and drain consisting of the multi-layer structure. The mechanism of off-current in short-channel vertical-type a-Si FET is discussed. The multilayered structure is incorporated in an attempt to reduce the back gate effect. The preliminary experimental results are also presented.

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Improved off-Characteristics of a-Si Vertical-Type Mosfets

  • Hiroyuki Okada (a1), Jun'ichi Sakano (a1), Shunri Oda (a1) and Masakiyo Matsumura (a1)

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