Hostname: page-component-77c89778f8-sh8wx Total loading time: 0 Render date: 2024-07-17T14:08:56.901Z Has data issue: false hasContentIssue false
  • English
  • Français

Impact of Gate Process Technology on EOT of HfO2 Gate Dielectric

Published online by Cambridge University Press:  01 February 2011

Daewon Ha ,
Qiang Lu ,
Hideki Takeuchi ,
Tsu-Jae King ,
Katsunori Onishi ,
Young-Hee Kim  and
Jack C. Lee
Daewon Ha
Affiliation:
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA
Qiang Lu
Affiliation:
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA
Hideki Takeuchi
Affiliation:
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA
Tsu-Jae King
Affiliation:
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA
Katsunori Onishi
Affiliation:
Department of Electrical and Computer Engineering, University of Texas, Austin, TX, USA
Young-Hee Kim
Affiliation:
Department of Electrical and Computer Engineering, University of Texas, Austin, TX, USA
Jack C. Lee
Affiliation:
Department of Electrical and Computer Engineering, University of Texas, Austin, TX, USA
Get access

Abstract

To facilitate CMOS scaling beyond the 65 nm technology node, high-permittivity gate dielectrics such as HfO2 will be needed in order to achieve sub-1.3nm equivalent oxide thickness (EOT) with suitably low gate leakage, particularly for low-power applications. Polycrystalline silicon-germanium (poly-SiGe) is a promising gate material because it is compatible with a conventional CMOS process flow, and because it can yield significantly lower electrical gate-oxide thickness as compared with poly-Si. In this paper, the effects of the gate material (Si vs. SiGe) and gate deposition rate on EOT and gate leakage current density are investigated. Poly-Si0.75Ge0.25 gate material yields the lowest EOT and is stable up to 950°C for 30 seconds, providing 2 orders of magnitude lower leakage current compared to poly-Si gate material. A faster gate deposition rate (achieved by using S2H6 instead of SiH4 as the gaseous Si source) is also effective for minimizing the increases in EOT and leakage current with high-temperature annealing.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 765: Symposium D – CMOS Front-End Materials and Process Technology , 2003 , D2.2
Copyright
Copyright © Materials Research Society 2003

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1. International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2001.Google Scholar
2. Kang, L., Onishi, K., Jeon, Y., Lee, B.H., Kang, C., Qi, W.-J., Nieh, R., Gopalan, S., Choi, R., and Lee, J.C., International Electron Devices Meeting, Technical Digest, pp. 35–38, 2000.Google Scholar
3. Lee, W. C., King, T.-J., and Hu, C., 1998 Symposium on VLSI Technology, Digest of Technical Papers, pp. 190–191, 1998.Google Scholar
4. Tavel, B., Monsieur, F., Ribot, P., and Skotnicki, T., Proceedings of the 32nd European Solid-State Device Research Conference, pp. 127–130, 2002.Google Scholar
5. Lu, Q., Takeuchi, H., Meng, X., King, T.-J., Hu, C., Onishi, K., Cho, H.-J., and Lee, J., 2002 Symposium on VLSI Technology, Digest of Technical Papers, pp. 86–87, 2002.Google Scholar
6. Onishi, K., Kang, C.S., Choi, R., Cho, H.-J., Gopalan, S., Nieh, R., Krishnan, S., and Lee, J.C., 2002 Symposium on VLSI Technology, Digest of Technical Papers, pp. 22–23, 2002.Google Scholar
7. Quantum mechanical C-V simulator (http://www-device.eecs.berkeley.edu/qmcv), University of California, Berkeley.Google Scholar
8. Sze, S.M., Physics of Semiconductor Devices, 2nd ed. (John Wiley & Sons, 1981), p.402.Google Scholar