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Impact of Gate Process Technology on EOT of HfO2 Gate Dielectric

  • Daewon Ha (a1), Qiang Lu (a1), Hideki Takeuchi (a1), Tsu-Jae King (a1), Katsunori Onishi (a2), Young-Hee Kim (a2) and Jack C. Lee (a2)...

Abstract

To facilitate CMOS scaling beyond the 65 nm technology node, high-permittivity gate dielectrics such as HfO2 will be needed in order to achieve sub-1.3nm equivalent oxide thickness (EOT) with suitably low gate leakage, particularly for low-power applications. Polycrystalline silicon-germanium (poly-SiGe) is a promising gate material because it is compatible with a conventional CMOS process flow, and because it can yield significantly lower electrical gate-oxide thickness as compared with poly-Si. In this paper, the effects of the gate material (Si vs. SiGe) and gate deposition rate on EOT and gate leakage current density are investigated. Poly-Si0.75Ge0.25 gate material yields the lowest EOT and is stable up to 950°C for 30 seconds, providing 2 orders of magnitude lower leakage current compared to poly-Si gate material. A faster gate deposition rate (achieved by using S2H6 instead of SiH4 as the gaseous Si source) is also effective for minimizing the increases in EOT and leakage current with high-temperature annealing.

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Impact of Gate Process Technology on EOT of HfO2 Gate Dielectric

  • Daewon Ha (a1), Qiang Lu (a1), Hideki Takeuchi (a1), Tsu-Jae King (a1), Katsunori Onishi (a2), Young-Hee Kim (a2) and Jack C. Lee (a2)...

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