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Gate-Prior-To-Isolation Cmos-Technology with Through-The-Gate-Implanted Ultra-Thin Gate Oxides

Published online by Cambridge University Press:  10 February 2011

Udo Schwalke
Affiliation:
Infineon Technologies AG, Otto-Hahn-Ring 6, 81730 Munich, Germany
Christian Gruensfelder
Affiliation:
Infineon Technologies AG, Otto-Hahn-Ring 6, 81730 Munich, Germany
Alexander Gschwandtner
Affiliation:
Infineon Technologies AG, Otto-Hahn-Ring 6, 81730 Munich, Germany
Gudrun Innertsberger
Affiliation:
Infineon Technologies AG, Otto-Hahn-Ring 6, 81730 Munich, Germany
Martin Kerber
Affiliation:
Infineon Technologies AG, Otto-Hahn-Ring 6, 81730 Munich, Germany
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Abstract

We have realized direct-tunneling gate oxide (1.6nm) NMOS and PMOS transistors by means of through-the-gate-implantation in a comer parasitics-free shallow-trench-isolation CMOS technology. In order to take full advantage of in-situ cluster-tool processing and to preserve initial wafer-surface quality, the essential part of the MOS gate is fabricated prior to device isolation and through-the-gate-implantation is utilized for well- and channel doping. In addition, a fully-reinforced-gate-oxide-perimeter is provided and trench comer parasitics are eliminated by the advanced process architecture EXTIGATE without increasing process complexity.

Type
Research Article
Copyright
Copyright © Materials Research Society 1999

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References

REFERENCES

1 Momose, H. S., Ono, M., Yoshitomi, T., Ohguro, T., Nakamura, S., Saito, M. and Iwai, H., „Tunneling gate oxide approach to ultra-high current drive in small-geometry MOSFETs“, IEDM Techn. Digest, p.593 (1994)Google Scholar
2 Bryant, A., Haensch, W. and Mii, T., „Characteristics of CMOS device isolation for the ULSI age“, IEDM Tech. Digest, p. 671 (1994)Google Scholar
3 Ogura, T., Yamamoto, T., Saito, Y., Hayashi, Y. and Mogami, T., „A shallow trench isolation with SiN guard-ring for sub-quarter micron CMOS technologies“, Symp. on VLSI Tech. p. 210 (1998)Google Scholar
4 Miyashita, M., Itano, M., Imaoka, T., Kawanabe, I. and Ohmi, T., „Dependence of thin oxide films quality on surface microroughness“, Symp. on VLSI Tech. p. 45 (1991)Google Scholar
5 Momose, H.S., Nakamura, S., Ohguro, T., Yoshitomi, T., Morifuji, E., Morimoto, T., Katsumata, Y. and Iwai, H., „Study of the manufactoring feasibility of 1.5-nm direct-tunneling gate oxide MOSFET's: Uniformity, reliability and dopant penetration of the gate oxide“, IEEE Trans. Electron Devices 45, (3) p. 691 (1998)10.1109/16.661230Google Scholar
6 Schwalke, U., Kerber, M., Koller, K. and Jacobs, H., „EXTIGATE: The ultimate process architecture for submicron CMOS technologies“, IEEE Trans. Electron Devices 44, (11) p. 2070 (1997)10.1109/16.641386Google Scholar
7 Schwalke, U., Füldner, M., Zatsch, W., Bothe, K., Hadawi, D., Janssen, I. and Schon, P., „Through-the-gate implanted (TGI) CMOS technology with advanced shallow trench isolation“ Ext. Abstr. SSDM, p. 156 (Hiroshima, Japan, 1998)Google Scholar
8 Depas, M., Degraeve, R., Nigam, T., Groeseneken, G. and Heyns, M., „Reliability of ultra-thin gate oxide below 3nm in the direct tunneling regime“, Jpn. J. Appl. Phys. 36, p. 1602 (1997)10.1143/JJAP.36.1602Google Scholar