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From Process Assumptions to Development to Manufacturing

Abstract

A tool has been developed that can be used to characterize or validate a BEOL interconnect technology. It connects various process assumptions directly to electrical parameters including resistance. The resistance of narrow copper lines is becoming a challenging parameter, not only in terms of controlling its value but also understanding the underlying mechanisms. The resistance was measured for 45nm-node interconnects and compared to the theory of electron scattering. This work will demonstrate how valuable it is to directly link the electrical models to the physical on-wafer dimensions and in turn to the process assumptions. For example, one can generate a tolerance pareto for physical and or electrical parameters that immediately identifies those process sectors that have the largest contribution to the overall tolerance. It also can be used to easily generate resistance versus capacitance plots which provide a good BEOL performance gauge. Several examples for 45nm BEOL will be given to demonstrate the value of these tools.

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1. Sondheimer, E. H., Advances in Physics, 2001, 50 (6), 499537
2. Mayadas, A. F. and Schatzkes, M, Phys. Rev. B, 1970, 1 (4), 13821389
3. Rossnagel, S. M. and Kuan, T. S., JVST B, 2004, Vol. 22 (1), 240247
4. Standaert, T., Lustig, N., and Lu, N., to be published.
5. Sankaran, S., et al, Electron Devices Meeting, 2006, IEDM '06 International.

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