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From planar to vertical nanowires field-effect transistors

  • Guillaume Rosaz (a1) (a2), Bassem Salem (a1), Nicolas Pauc (a2), Pascal Gentile (a2), Priyanka Periwal (a1), Alexis Potié (a1), Thierry Baron (a1), L. Latu-Romain (a1) and S. David (a1)...

Abstract

The authors present the technological routes used to build planar and vertical gate all-around (GAA) field-effect transistors (FETs) using both Si and SiGe nanowires (NWs) and the electrical performances of the as-obtained components. Planar FETs are characterized in back gate configuration and exhibit good behavior such as an ION/IOFF ratio up to 106. Hysteretic behavior and sub-threshold slope values with respect to surface and oxide interface trap densities are discussed. Vertical devices using Si NWs show good characteristics at the state of the art with ION/IOFF ratio close to 106 and sub-threshold slope around 125 mV/decade while vertical SiGe devices also obtained with the same technological processes, present an ION/IOFF ratio from 103 to 104but with poor dynamics which can be explained by the high interface traps density.

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Keywords

From planar to vertical nanowires field-effect transistors

  • Guillaume Rosaz (a1) (a2), Bassem Salem (a1), Nicolas Pauc (a2), Pascal Gentile (a2), Priyanka Periwal (a1), Alexis Potié (a1), Thierry Baron (a1), L. Latu-Romain (a1) and S. David (a1)...

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