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Electrical Characterization of a Double Barrier Direct Tunneling Diode Structure

  • E. M. Dons (a1), C. S. Skowronski (a1) and K. R. Farmer (a1)

Abstract

We report the electrical characterization of a direct tunneling diode structure that incorporates a multilayer dielectric. The dielectric consists of a stack of two thermally grown, ultrathin SiO2 layers, each ∼3.5 rin thick, separated by a deposited, continuous, undoped, ultrathin nanocrystalline Si layer ∼5.0 nm thick. Electrical measurements of this structure are reported for both n-type and p-type Si substrates. We find that the room temperature transport through this structure is accounted for by describing the intermediate Si layer as a quantum well with a continuum of states, and by otherwise assuming bulk properties for the ultrathin layers, such as the existence of a bandgap in the Si well and the usual Si-SiO2 interface potential barrier height at all interfaces. This structure is expected to be useful as the active dielectric in nonvolatile memory devices.

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1 Dons, E. M., Skowronski, C. S., Farmer, K. R., Appl. Phys. Lett. 73, 3712 (1998).10.1063/1.122872
2 Farmer, K. R., Andersson, M. O., Engström, O., Appl. Phys. Lett. 60, 730 (1992).10.1063/1.106551
3 Tiwari, S., Rana, F., Hanafi, H., Hartstein, A., Crabbe, E. F., Chan, K., Appl. Phys. Lett. 68, 1377 (1996).10.1063/1.116085

Electrical Characterization of a Double Barrier Direct Tunneling Diode Structure

  • E. M. Dons (a1), C. S. Skowronski (a1) and K. R. Farmer (a1)

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