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The Effects of the LDD process on Short-channel effects in Nanoscale Charge Trapping Devices

Published online by Cambridge University Press:  01 February 2011

Moon Kyung Kim
Affiliation:
mkk23@cornell.edu, Cornell University, Electrical and Computer Engineering, 2250N Triphammer RD L3E, Ithaca, NY, 14850, United States, 607-592-2940
SooDoo Chae
Affiliation:
sudu@samsung.com, Samsung Electronics Co., Semiconductor Business, Yongin-City, Kyunggi-Do, N/A, Korea, Republic of
Chung Woo Kim
Affiliation:
cw_kim@samsung.com, Samsung Electronics Co., Semiconductor Business, Yongin-City, Kyunggi-Do, N/A, Korea, Republic of
Joo Yeon Kim
Affiliation:
joo@mail.uc.ac.kr, Ulsan college, School of Electricity & Electronics, Ulsan, 682-715, N/A, Korea, Republic of
Jo-won Lee
Affiliation:
jwlee@nanotech.re.kr, Tera-level Nano Devices, Seoul, N/A, Korea, Republic of
Sandip Tiwari
Affiliation:
st222@cornell.edu, Cornell University, Electrical and Computer Engineering, Ithaca, NY, 14850, United States
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Abstract

In the use of single/few electrons in distributed storage for non-volatile, low power, and fast memories, providing statistical reproducibility at the nanoscale is a key challenge since relative variance has dependence and the devices operate with limited number of storage sites. We have used defects at interfaces of dielectrics to evaluate this reproducibility and the performance of memories. These experiments show that nearly 100 electrons can be stored at 30 nm dimensions, sufficient for reproducibility, and that a minimum of tunneling oxide thickness is required to assure reliable retention characteristics. Different tunneling oxide thicknesses and the effect of LDD process are investigated to draw these conclusions.

Type
Research Article
Copyright
Copyright © Materials Research Society 2007

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