The asymmetric amorphous silicon thin film transistors are fabricated and exposed to various stress environments. A visible light illumination of 200,000 Ix and gate bias of 30 V are applied to both asymmetric and widely used symmetric a-Si TFT's. It is observed that the leakage current of asymmetric structure, where only one electrode is fully overlapped by gate electrode, is much less than that of symmetric one. The visible light illumination as well as gate bias stress do not degrade the leakage current of the asymmetric a-Si TFT's, while the leakage current in die symmetric TFT's are increased considerably due to the stress. Also, the degree of degradation in the threshold voltage, the field effect mobility and the subthreshold slope of asymmetric TFT's are relatively much less than that of conventional symmetric TFT's.