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Effective Dielectric Thickness Scaling for High-K Gate Dielectric Mosfets

  • Krishna Kumar Bhuwalka (a1), Nihar R. Mohapatra (a1), Siva G. Narendra (a1) and V Ramgopal Rao (a1)

Abstract

It has been shown recently that the short channel performance worsens for high-K dielectric MOSFETs as the physical thickness to the channel length ratio increases, even when the effective oxide thickness (EOT) is kept identical to that of SiO2. In this work we have systematically evaluated the effective dielectric thickness for different Kgate to achieve targeted threshold voltage (Vt), drain-induced barrier lowering (DIBL) and Ion/Ioff ratio for different technology generations down to 50 nm using 2-Dimensional process and device simulations. Our results clearly show that the oxide thickness scaling for high-K gate dielectrics and SiO2 follow different trends and the fringing field effects must be taken into account for estimation of effective dielectric thickness when SiO2 is replaced by a high-K dielectric.

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1. Taur, Y., Mii, Y. J., Frank, D. J., Wong, H. S., Buchanan, D. A., Wind, S. J., Rishton, S. A., Sai-Halasz, G. A. and Nowak, E. J., “CMOS scaling into the 21st century: 0.1μm and beyond”, IBM Journal of Research and Development, Vol. 39, No. 12, 1995.
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Effective Dielectric Thickness Scaling for High-K Gate Dielectric Mosfets

  • Krishna Kumar Bhuwalka (a1), Nihar R. Mohapatra (a1), Siva G. Narendra (a1) and V Ramgopal Rao (a1)

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