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Doping process issues for Sub-0.1 μm generation MOSFETs

  • Toshihiro Sugii (a1), Sergey Pidin (a1), Youichi Momiyama (a1), Ken- ichi Goto (a1), Takuji Tanaka (a1), Tomonari Yamamoto (a1), Toshirou Futatugi (a1) and Masatak Kase (a2)...

Abstract

To meet the market demands for higher performance LSIs, traditional scaling has been aggressively pursued and has enjoyed great success over the 0.1-μm generations. To maintain continued growth of CMOS performance beyond the 0.1-μm generation, key issues originating from traditional scaling are addressed from the viewpoint of the doping processes (channel engineering, high-activation, and gate- electrode structure) in this paper.

To meet the acceleration in gate-length miniaturization, short-channel effects must be suppressed at a low threshold voltage by using aggressive channel engineering. A channel-impurity profile must be optimized two-dimensionally, not uniformly or one-dimensionally. Channel engineering using tilted-channel implantation (TCI) with Indium is demonstrated.

Traditional scaling results in large variations of threshold voltage due to the statistical-impurity variation in a channel region. We studied the effect of the above channel engineering on threshold voltage fluctuation caused by a statistical- dopant variation by measurement and simulation. It is reported that the two-dimensionally optimized channel profile enhances threshold-voltage fluctuation even if the implantation process variation is negligible.

As CMOS device scales, reduction of parasitic resistance becomes very important for a high performance operation. Resistance at extension egde and contact resistance at silicide-Si interface are dominant factors.The traditional approach is to use a higher RTA temperature and a shorter RTA time. The ultimate RTA is laser annealing. We will demonstrate the laser annealing process with an ultra-low contact resistance of 4 × 10−8 Ω-cm2.

By integrating the above technologies, ultra-thin gate insulators, and reduction in gate to source/drain overlap length, we can establish front-end process for sub-0.1 μm generations.

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References

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Doping process issues for Sub-0.1 μm generation MOSFETs

  • Toshihiro Sugii (a1), Sergey Pidin (a1), Youichi Momiyama (a1), Ken- ichi Goto (a1), Takuji Tanaka (a1), Tomonari Yamamoto (a1), Toshirou Futatugi (a1) and Masatak Kase (a2)...

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