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Current Status of Fabrication and Integration of Ferroelectric-Gate Fet's

Published online by Cambridge University Press:  10 February 2011

Hiroshi Ishiwara
Hiroshi Ishiwara*
Affiliation:
Frontier Collaborative Research Center, Tokyo Institute of Technology 4259 Nagatsuda, Midoriku, Yokohama 226–8503Japan
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Abstract

Current status of fabrication and integration of ferroelectric-gate FET's is reviewed. Novel applications of ferroelectric-gate FET's are first discussed, which include a single-transistor-cell-type digital memory, reconfigurable LSI's, and an analog memory for an artificial neural network. In the neural network application, fabrication and basic operation of a pulse-frequency-modulation-type adaptive-learning neuron circuit are described as well as an SOI (silicon-on-insulator)-type FET array for synaptic connection is proposed.

Then. data retention characteristics of ferroelectric-gate FET's with MFIS (M : metal, F : ferroelectric, I : insulator (buffer layer), S : semiconductor) and MFMIS structures are discussed. It is shown that the important factors to improve the retention characteristics are (1) increase of the buffer layer capacitance, (2) decrease of the leakage current of both the ferroelectric film and buffer layer, and (3) optimization of the area ratio between the MFM and MIS parts in the MFMIS structure. Based on these considerations, MFMIS-FET's were fabricated using a stacked buffer layer of SrTa2O6/SiON; a current on/off ratio larger than 103 was obtained at a retention time of 10 hours.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 596: Symposium Y – Ferroelectric Thin Films VIII , 1999 , 427
Copyright
Copyright © Materials Research Society 2000

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