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Current Issues and Future Trends in CMP Consumables for Oxide and Metal Polish

  • M. Moinpour (a1) and A. Philipossian (a1)


The recent advent of Chemical Mechanical Planarization (CMP) as a major process technology has had a significant impact on the semiconductor industry. Oxide CMP is a technology enabler for logic and DRAM devices with feature sizes less than (or equal to) 0.75 micrometer [1]. Similarly, tungsten CMP has become a technology enabler for 0.35 micron devices [2,3], and current trends indicate that it will continue to play a major role in future generations of IC technologies [4,5]. CMP can also provide a technological advantage in front-end process modules such as Shallow Trench Isolation [6].



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[1] Renteln, P., Thomas, M. and Pierce, J., VMIV Proc., p. 57,1991.
[2] Rutten, M., Huynh, C., SRC Topical Conf. in CMP, July 1995.
[3] Kaufman, F., et. al., ”Chemical-Mechanical Polishing for Fabricating Patterned WMetal Features as Chip Interconnects”, J. Electrochem. Soc., Vol.138, No. 11., p. 3460, Nov., 1991.
[4] Sivaram, S., Bath, H., Leggett, R., Maury, A., Monnig, K., and Tolles, R., Solid State Tech., p. 87, 1992.
[5] Furumura, Y., et. al., ”CMP Roadmap for a Large Diameter Wafer”, Proceedings 24th Symposium on ULSl Ultra Clean Technology, Tokyo, p191, March 1995.
[6] Davari, B., Koburger, C., Schutz, R. et al., IEDM Tech. Digest, p. 61, 1989.
[7] Patrick, W. et. al., ”Application of Chemical Mechanical Polishing to the Fabrication of VLSI Circuit Interconnections” J. Electrochem. Soc., Vol.138, p. 1778, 1991.
[8] Cook, L., Wang, J., James, D. and Sethuraman, A., Semiconductor International,p. 141, Nov. 1995.
[9] Scherber, D. and Neville, M., Proceedings of the Symposium on Planarization Technology: CMP, Semicon West, 1994.
[10] Jairath, R., et. al., ”Chemical and Mechanical polishing: ProcessManufacturability”, Solid State Technology, p. 71, July 1994.
[11] Steigerwald, J., et al, J. Electrochem. Soc., 1995.
[12] German, R. Powder Metallurgy Science , (Princeton: Metal Powder Industry, 1984) pp. 954.
[13] Shaw, A., “Selection of Particle Sizing Technology for CMP slurries,” Abstract: Spring Meeting Materials Research Society, p. 203, 1995.
[14] Hayashi, Y., Proceedings 24th Symposium on ULSI Ultra Clean Technology, Tokyo, p. 182, March 1995.
[15] Tomozawa, M. et. al. “Effect of Pad Characteristics on Oxide Polishing Performance,” SRC Topical Conf. in CMP, July 1995.
[16] Jeong, H., Karaki-Doy, T. et. al., “New polishing by mechanical and chemical polishing techniques insensitive to pattern-topography for VLSI wafer,” Proceedings of MicroProcess, p. 121,1994.

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Current Issues and Future Trends in CMP Consumables for Oxide and Metal Polish

  • M. Moinpour (a1) and A. Philipossian (a1)


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