III-nitride structures on Si are of great technological importance due to the availability of large area, epi ready Si substrates and the ability to heterointegrate with mature silicon micro and nanoelectronics. High voltage, high power density, and high frequency attributes of GaN make the III-N on Si platform the most promising technology for next-generation power devices. However, the large lattice and thermal mismatch between GaN and Si (111) introduces a large density of dislocations and cracks in the epilayer. Cracking occurs along three equivalent {1−100} planes which limits the useable device area. Hence, efforts to obtain crack-free GaN on Si have been put forth with the most commonly reported technique being the insertion of low temperature (LT) AlN interlayers. However, these layers tend to further degrade the quality of the devices due to the poor quality of films grown at a lower temperature using metal organic chemical vapor deposition (MOCVD). Our substrate engineering technique shows a considerable improvement in the quality of 2 μm thick GaN on Si (111), with a simultaneous decrease in dislocations and cracks. Dislocation reduction by an order of magnitude and crack separation of > 1 mm has been achieved. Here we combine our method with step-graded AlGaN layers and LT AlN interlayers to obtain crack-free structures greater than 3.5 μm on 2” Si (111) substrates. A comparison of these film stacks before and after substrate engineering is done using atomic force microscopy (AFM) and optical microscopy. High electron mobility transistor (HEMT) devices developed on a systematic set of samples are tested to understand the effects of our technique in combination with crack reduction techniques. Although there is degradation in the quality upon the insertion of LT AlN interlayers, this degradation is less prominent in the stack grown on the engineered substrates. Also, this methodology enables a crack-free surface with the capability of growing thicker layers.