The fabrication of high yielding ferroelectric capacitors on CMOS wafers is difficult due to the negative impact of post-capacitor process steps, especially the interlayer dielectric and the metal interconnect sinter. Proper selection of the process for each layer of the capacitor structure is necessary to minimize hysteresis damage to the ferroelectric capacitors during their construction. The authors fabricated integrated PZT capacitors on blank silicon wafers using lift off processes for the bottom and top electrodes and a combination titanium dioxide/silicon dioxide dielectric between the ferroelectric capacitors and the metal interconnect layer. A 15 minute nitrogen anneal at 450 degrees centigrade after the metal interconnect patterning did not damage the capacitor hysteresis loops. Statistical testing of over 700 capacitors for shorts indicated a defect rate of 127 defects per square centimeter. This is sufficiently low enough to generate 50% yield in a production 64Kbit double-sided-sense nonvolatile memory. At 3.5V, the capacitors generated 14.0 microcoulombs per square centimeter with a standard deviation of 2.3 microcoulombs per square centimeter. The authors have set a target for future lots of 20 defects per square centimeter with 32 microcoulombs per square centimeter at 2.0V with a standard deviation of 1.6 microcoulombs per square centimeter.