As technology progresses, the need for thinner Cu diffusion barrier caps is becoming more important, and it is advantageous if these barriers have low dielectric constants (κ). Towards this end, we characterized Cu penetration in several thin (35 nm to 70 nm) dielectrics, including silicon nitrides, silicon oxynitrides, an amorphous hydrogenated carbon film, and a methyl silsesquioxane layer. Metal Insulator Silicon (MIS) structures were used as the test vehicle. The barrier dielectrics were deposited on 100 nm thermal oxide which was grown on 2 Ω-cm, n-type Si wafers. After the deposition of 50 nm TEOS capping layers, both Al and Cu dots were evaporated on each wafer through a mask. Both Al and Cu dot samples were stressed at +2.7 MV/cm at 300°C for 10 minutes. For Cu dots, the applied stress pushed Cu ions into the dielectric stack. Stressing Al dots characterized the effects of the stress on the dielectric stacks and the quantity of Na ions in the films. Since C-V shifts are subject to stress-related instabilities in the interfaces as well as within the dielectrics themselves, triangular voltage sweep (TVS) was used after the applied stress to measure the concentration of Cu which reached the underlying thermal oxide film. The sensitivity of the TVS test with the structures used is about 5×109/cm2. Secondary ion mass spectroscopy (SIMS) analyses were performed on some of these samples to verify the electrical results.