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Characterization of Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) FETs Using (Sr,Sm)0.8Bi2.2Ta2O9 (SSBT) Thin Films

Published online by Cambridge University Press:  01 February 2011

Hirokazu Saiki  and
Eisuke Tokumitsu
Hirokazu Saiki
Affiliation:
Precision and Intelligence Laboratory, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama, 226–8503, Japan
Eisuke Tokumitsu
Affiliation:
Precision and Intelligence Laboratory, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama, 226–8503, Japan IT-21 Center, Research Institute of Electrical Communication, Tohoku University, 2–1–1 Katahira, Aoba-ku, Sendai, 980–8577, Japan
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Abstract

We have fabricated and characterized Pt (60nm) / (Sr,Sm)0.8Bi2.2Ta2O9 (SSBT, 130nm) / Pt (60nm) / Ti (10nm) / SiO2 (10nm) / p-Si (MFMIS:metal-ferroelectric-metal-insulator-semiconductor) structure FETs. The area ratio, the ratio of SSBT capacitor area to SiO2 capacitor, is varied from 1 to 15 in the MFMIS-FETs. It is demonstrated that MFMIS-FETs with area ratio of 6 have memory window of 0.5V with supply voltage of 5 V. Dependence of memory window on the area ratio is discussed.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 786: Symposium E – Fundamentals of Novel Oxide/Semiconductor Interfaces , 2003 , E9.8/C9.8
Copyright
Copyright © Materials Research Society 2004

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References

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