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Barium Strontium Titanate Capacitors for Embedded Dram

  • Peter Zurcher (a1), C.J. Tracy (a1), R.E. Jones (a2), P. Alluri (a2), P.Y. Chu (a2), B. Jiang (a2), M. Kim (a1), B.M. Melnick (a2), M.V. Raymond (a2), D. Roberts (a2), T.P. Remmel (a1), T.L. Tsai (a1), B.E. White (a2), S. Zafar (a2) and S.J. Gillespie (a2)...


Long recognized as the best potential solution to the continued scaling of the onetransistor/one-capacitor standalone dynamic random access memory (DRAM) beyond a gigabit, barium strontium titanate (BST) and other high permittivity dielectrics are fast becoming enablers to embedding large amounts of memory into a high performance logic process. System requirements such as granularity, bandwidth, fill frequency, and power pose major challenges to the use of high density standalone DRAM, leading to the current push for embedded solutions where very wide buses are possible. As a result, projected embedded memory sizes are rapidly approaching that of the standalone products, and with the high wafer cost of the combined logic plus memory process, bit cell scaling is critical. The BST memory cell, with its low thermal budget processing, very high charge storage density, and high conductivity metal electrodes has the potential to be efficiently embedded with traditional logic flows if the materials and integration challenges of the required three dimensional (3D) bit cell capacitors can be solved. BST materials properties such as dielectric relaxation, interface capacitance, and resistance degradation and their impact on capacitor scaling will be reviewed along with the electrode materials issues associated with certain 3D capacitor designs. The scaling limits of BST bit cells in the deep sub-micron regime will be discussed.



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