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The Application of Solid Source Diffusion in the Vertical Replacement-Gate (VRG) MOSFET

Published online by Cambridge University Press:  17 March 2011

Sang-Hyun Oh ,
J.M. Hergenrother ,
Don Monroe ,
T. Nigam ,
F.P. Klemens ,
A. Kornblit ,
W.M. Mansfield ,
F.H. Baumann ,
H.J. Gossmann  and
C.A. King
...Show all authors
Sang-Hyun Oh
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA
J.M. Hergenrother
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA
Don Monroe
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA
T. Nigam
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA
F.P. Klemens
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA
A. Kornblit
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA
W.M. Mansfield
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA
F.H. Baumann
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA
H.J. Gossmann
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA
C.A. King
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA
R.N. Kleiman
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA
H-H. Vuong
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA
G.R. Weber
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA
C.S. Rafferty
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA
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Abstract

We discuss the first use of solid source diffusion (SSD) to form shallow, self-aligned SDEs in a novel device known as the Vertical Replacement-Gate (VRG) MOSFET. This is the only MOSFET ever built that combines 1) a gate length controlled precisely through a deposited film thickness, independently of lithography and etch, and 2) a high-quality gate oxide grown on a single-crystal Si channel. The use of SSD in this novel geometry allows us to transform the precise gate length control afforded by the VRG process into precise, lithography-independent channel length control. In the VRG-nMOS process, silicon nitride offset spacers separate the phosphosilicate glass (PSG) SSD dopant sources from the polysilicon gate. These offset spacers, whose critical dimensions are also controlled by film thicknesses, allow us to precisely tune the gate-source and gate-drain overlaps in order to optimize the capacitance/series resistance tradeoff. These parasitic overlap capacitances have precluded the high-frequency operation of many previous vertical MOSFETs. In this paper, we discuss the SIMS and sheet resistance characterization of shallow phosphorus junctions formed in one-dimensional SSD experiments. We will also discuss the scanning capacitance characterization of two-dimensional doping profiles of VRG-nMOSFETs with gate lengths down to 50 nm.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 610: Symposium B – Si Front End Processing - Physics & Technology..II , 2000 , B3.2
Copyright
Copyright © Materials Research Society 2000

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