Hostname: page-component-5d59c44645-l48q4 Total loading time: 0 Render date: 2024-03-02T23:48:24.291Z Has data issue: false hasContentIssue false

A Self-Aligned Silicide Process for Thin Silicon-on-Insulator MOSFETs and Bulk MOSFETs with Shallow Junctions

Published online by Cambridge University Press:  15 March 2011

G. M. Cohen
Affiliation:
IBM T. J. Watson Research Center, Yorktown Heights, NY 10598
C. Cabral Jr.
Affiliation:
IBM T. J. Watson Research Center, Yorktown Heights, NY 10598
C. Lavoie
Affiliation:
IBM T. J. Watson Research Center, Yorktown Heights, NY 10598
P. M. Solomon
Affiliation:
IBM T. J. Watson Research Center, Yorktown Heights, NY 10598
K.W. Guarini
Affiliation:
IBM T. J. Watson Research Center, Yorktown Heights, NY 10598
K.K. Chan
Affiliation:
IBM T. J. Watson Research Center, Yorktown Heights, NY 10598
R.A. Roy
Affiliation:
IBM T. J. Watson Research Center, Yorktown Heights, NY 10598
Get access

Abstract

We discuss a modified self-aligned silicide (salicide) process that uses a silicon cap to reduce the substrate silicon consumption by 50% as compared with a conventional salicide process. We have used a metal-silicon mixture to form the metal-rich phase reliably in the first anneal. After etching the unreacted mixture we deposit a silicon cap. This forces the metal to react with the silicon cap as well as with the substrate during the second anneal, thus minimizing silicon consumption from the substrate. The unreacted portion of the silicon cap is selectively etched, leaving a structure with a raised source and drain. We expect this process to be useful for forming silicide on shallow junctions and thin SOI films, where silicon consumption is constrained.

Type
Research Article
Copyright
Copyright © Materials Research Society 2002

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

References:

1. Wong, H.-S. P., Frank, D.J., and Solomon, P.M., International Electron Device Meeting (IEDM), p. 407, (1998).Google Scholar
2. Wolf, S., in Silicon processing for the VLSI Era, Vol. 3, (Lattice Press, Sunset Beach, CA, 1995), p. 208.Google Scholar
3. Su, Lisa T., Sherony, M.J., Hu, H., Chung, J.E., Antoniadis, D. A., Electron Device Letters, 15(9), 363, (1994).Google Scholar