Published online by Cambridge University Press: 31 January 2011
Poly-SiGe has quite some potential as structural MEMS layer for CMOS-MEMS integration. However, the contact resistance between SiGe MEMS and top CMOS metal should be low to avoid parasitic effects that would reduce the system performance. In this paper, a new and simple approach is proposed to achieve a low contact resistance between a top CMOS interconnect and a boron doped poly-SiGe MEMS layer deposited at 450 °C. The use of a 20 nm soft sputter etch in combination with a Ti-TiN (5-10 nm) interlayer results in a contact resistivity of 6.2 ± 0.4 × 10-7 Ωcm2 that is lower than previously reported. The uniformity of the contact resistivity across the wafer is also better than the state-of-the-art value.
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