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Issues and Challenges of Chemical Mechanical Polishing for Nano-scale Memory Manufacturing

Published online by Cambridge University Press:  31 January 2011

Choon Kun Ryu
Affiliation:
ckryu@krpost.net, Hynix Semiconductor Inc., R&D Division, Ichon, Korea, Republic of
Jonghan Shin
Affiliation:
jonghan.shin@hynix.com, Hynix Semiconductor Inc., R&D Division, Ichon, Korea, Republic of
Hyungsoon Park
Affiliation:
hyungsoon.park@hynix.com, Hynix Semiconductor Inc., R&D Division, Ichon, Korea, Republic of
Nohjung Kwak
Affiliation:
nohjung.kwak@hynix.com, Hynix Semiconductor Inc., R&D Division, Ichon, Korea, Republic of
Kwon Hong
Affiliation:
kwon.hong@hynix.com, Hynix Semiconductor Inc., R&D Division, Ichon, Korea, Republic of
Sungki Park
Affiliation:
sungki.park@hynix.com, Hynix Semiconductor Inc., R&D Division, Ichon, Korea, Republic of
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Abstract

As the design rule of memory devices is scaled down to nanoscale, the number of the CMP process has increased considerably due to the complexity of integration scheme. The CMP for isolation has increased significantly because the isolation process of metal contact plugs and damascene metallization at nanoscale has been successfully enabled by the CMP. The CMP selectivity, which depends strongly on the chemistry of the slurry, must be tuned for the various new materials. Recently, in order to get over the limitation in lateral shrinkage of the memory device, several emerging applications have been investigated extensively. A vertical integration needs the new CMP process such as high removal rate Cu CMP. Next generation memories need the CMP process for new materials such as GeSbTe, conductive oxide, and magnetic materials. Since any nano-size scratch will be a killer defect at the nanoscale memory, both the CMP equipment and the consumables must be maintained with tighter degree of control specifications.

Type
Research Article
Copyright
Copyright © Materials Research Society 2009

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