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Hot Carrier Reliability in Sub-0.1 μm nMOSFET Devices

Published online by Cambridge University Press:  15 February 2011

Samar K. Saha
Samar K. Saha*
Affiliation:
Advanced Process Development, Silicon Systems, Santa Cruz, CA 95060, saha@scz.ssil.corm
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Abstract

This paper presents a systematic investigation of the hot-carrier effect in deep sub-micron silicon nMOSFET devices. A Hydrodynamic model for semiconductors was used to simulate the local carrier heating and the non-local transport phenomena in nMOSFETs of effective channel lengths 41, 66, 96, and 126 nrn under various biasing conditions. Test structures for device simulation were generated by using a super-steep retrograde channel profile with subsurface peak concentration of l×1018 cm−3, and a gate oxide thickness of 3 nm. Superb MOSFET device characteristics were obtained for all devices. The simulation results show a significant decrease in substrate current, electron impact ionization rate, and peak electron temperature near the drain end of the channel with the decrease in supply voltage. The distribution of electrons into the substrate due to local electron heating is shown to be responsible for hot-carrier reliability in ultra-short channel silicon nMOSFET devices.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 428: Symposium L – Materials Reliability in Microelectronics VI , 1996 , 379
Copyright
Copyright © Materials Research Society 1996

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