The purpose of this paper is to review the current status of and to discuss key technological issues relative to GaAs integrated circuit contact and interconnect technology. Rapid progress and performance advantages exhibited by GaAs MSI circuits in both ultrahigh speed and low power dissipation has recently provided the motivation for the development of GaAs large-and very-large-scale integration (LSI and VLSI). The complexity, density and small feature size requirements of high speed LSI and VLSI places severe demands on GaAs contact and interconnect technology with respect to yield, reliability and performance.

The key device used today in GaAs integrated circuits is the depletion-mode Schottky barrier field effect transistor. Results on the optimization of GaAs field effect transistor Schottky barriers and ohmic contacts using X-ray photoelectron spectroscopy and Auger electron spectroscopy surface analysis techniques in conjunction with thermal reliability studies of various metal systems on GaAs will be presented. The established reliability for GaAs integrated circuits with a goldbased metallization system has been shown to have a mean time to failure of more than 109 h at room temperature.

The microcircuit lithography requirements of GaAs LSI and VLSI rely heavily on lift-off and dry etch replication techniques. Several high yield techniques, which have been specifically developed for GaAs, will be described. Finally, recent trends in GaAs device research relative to new non-alloyed contacts and high temperature Schottky barriers will be presented.