Hostname: page-component-8448b6f56d-c47g7 Total loading time: 0 Render date: 2024-04-15T22:41:17.827Z Has data issue: false hasContentIssue false

The Effect of Pad Properties on Planarity in a CMP Process

Published online by Cambridge University Press:  01 February 2011

Hoyoung Kim
Affiliation:
Process Development Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Giheung-Eup, Yongin-City, KOREA
Dong-Woon Park
Affiliation:
Process Development Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Giheung-Eup, Yongin-City, KOREA
Chang-Ki Hong
Affiliation:
Process Development Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Giheung-Eup, Yongin-City, KOREA
Woo-Sung Han
Affiliation:
Process Development Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Giheung-Eup, Yongin-City, KOREA
Joo-Tae Moon
Affiliation:
Process Development Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Giheung-Eup, Yongin-City, KOREA
Get access

Abstract

This study presents the effect of pad properties, such as elastic modulus and surface roughness, on planarity in a CMP process. A systematic method to measure planarization length, which represents the die-scale planarity in a quantitative manner, has been proposed. It has been shown that the planarization length is highly dependent on the bulk modulus of the pad. The effect of elastic modulus and roughness of the pad on dishing amount, which represents the feature-scale planarity, has been shown. Dishing amount is determined by the elastic modulus of the superficial layer of the pad, which is typically tens of microns thick, rather than by the bulk elastic modulus of the pad. A double layer pad model has been proposed based on the observed results, which can explain that the dishing amount is reduced by increasing elastic modulus of the pad superficial layer, or by decreasing the surface roughness of the pad.

Type
Research Article
Copyright
Copyright © Materials Research Society 2003

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1. Runnels, S. R., “Feature-Scale Fluid-Based Erosion Modeling for Chemical-Mechanical Polishing,” J. Electrochem. Soc., Vol. 141, No. 7, pp.19001904 (1994)Google Scholar
2. Yang, L., “Modeling CMP for Copper Dual Damascene Interconnects,” Solid State Technology, pp. 111121 (2000)Google Scholar
3. Lai, J., Saka, N., and Chun, J., “Evolution of Copper-Oxide Damascene Structures in Chemical Mechanical Polishing,” J. Electrochem. Soc., Vol. 149, No. 1, pp. G31–G40 (2002)Google Scholar
4. Grillaert, J. et al. , “Modeling Step Height Reduction and Local Removal Rates Based on Pad-Substrate Interation,” Proc. of CMP-MIC, pp. 7986 (1998)Google Scholar
5. Boning, D., Ouma, D., “Modeling and Simulation,” Chemical Mechanical Polishing in Silicon Processing, Academic Press, pp.89118 (2000)Google Scholar
6. Lefevre, P., Gonzales, A., Brown, T., Martin, G., Tugbawa, T., Park, T., Boning, D., Gostein, M., and Nguyen, J., “Direct Measurement of Planarization Length for Copper CMP Processes Using a Large Pattern Test Mask,” Mat. Res. Soc. Symp. Proc., Vol. 671, pp. M4.4.1–M4.4.6 (2001)Google Scholar