Hostname: page-component-7479d7b7d-767nl Total loading time: 0 Render date: 2024-07-11T04:26:09.748Z Has data issue: false hasContentIssue false
  • English
  • Français

Dry Etching for Nanometer-Scale Fabrication

Published online by Cambridge University Press:  21 February 2011

Richard E. Howard
Richard E. Howard*
Affiliation:
AT&T Bell Laboratories Room 4E-332 Holmdel, NJ 07733
Get access

Abstract

Conventional integrated circuit fabrication is currently making the transition from wet to dry etching in the effort to shrink feature sizes to about 1 micron. These plasma etching techniques, though, are not limited to micron dimensions; devices and structures smaller than 100 nm can be made. Using e-beam lithography and reactive ion etching, patterns down to about 20 nm have been made in tri-level stencils and in semiconductor substrates. Working silicon MOSFETs with gate widths down to about 30 nm have also been made. These MOSFET devices are so small that individual electron trapping events can be observed. These devices are being studied to give a better understanding of the physics of electronic conduction in small devices and better define the limits of microfabrication.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 38: Symposium F – Plasma Synthesis and Etching of Electronic Materials , 1984 , 247
Copyright
Copyright © Materials Research Society 1985

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

[1] Howard, R.E., Prober, D.E., “Nanometer-Scale Fabrication Techniques,” in VLSI Electronics: Microstructure Science, Vol.5, Einspruch, N., ed., Academic Press, (1982).Google Scholar
[2] Craighead, H.G., Howard, R.E., Jackel, L.D., Mankiewich, P.M., “10 nm Linewidth Lithography on GaAs,” Appl. Phys. Lett., vol.42, p. 38, (1983).Google Scholar
[3] Muray, A. and Isaacson, M., “Fabrication of Aperatures, Slots, and Grooves at the 8–80 nm scale in Silicon and Metal Films,” I. Vac. Sci. Technol., vol. B1, p. 1091, (1983).Google Scholar
[4] Howard, R.E., Craighead, H.G., Jackel, L.D., Mankiewich, P.M., “Electron Beam Lithography from 20 to 120 keV with a High Quality Beam,” J. Vac. Sci. Technol., vol. B1, p. 1101, (1983).CrossRefGoogle Scholar
[5] Neill, T.R. and Bull, C.J., “High Voltage Electron Lithography,” Electronic Lett., vol.16, p. 621, (1980).Google Scholar
[6] Moran, J.M., Maydan, D., “High Resolution, Steep Profile Resist Patterns,” J. Vac. Sci. Technol., vol.16, p. 1620, (1980).Google Scholar
[7] Jackel, L.D., Howard, R.E., Hu, E.L., Tennant, D.M., Grabbe, P., “50-nm Silicon Structures Fabricated with Trilevel Electron Beam Resist and Reactive-Ion-Etching,” Appl. Phys. Lett., vol.39, p. 268, (1981).Google Scholar
[8] Watts, R.K., Fichtner, W., Fuls, E.N., Thibault, L.R., Johnston, R.L., “Electron-Beam Lithography for Small MOSFET's,” IEEE Trans. Electron Dev., vol. ED-28, p. 1338, (1981).Google Scholar
[9] Polyimide XU218, CIBA-GEIGY Corp., Ardsley, NY. 10502.Google Scholar
[10] Grabbe, P., Hu, E.L. and Howard, R.E., “Tri-level Lift-off Process for Refractory Metals”, J. Vac. Sci. Technol., vol.21, p. 33, (1982).Google Scholar
[11] Hu, E.L., Howard, R.E., Grabbe, P., Tennant, D.M., “Ion Beam Processing Using Metal-on- Polymer Masks,” J. Electrochem. Soc., vol.130, p. 1171, (1983).CrossRefGoogle Scholar
[12] Skocpol, W.J., Jackel, L.D., Howard, R.E., Behringer, R.E., Fetter, L.A., Tennant, D.M., Mankiewich, P.M., “Search for Flux Periodicity in Quasi-One-Dimensional AuPd, AuGe, and Si MOSFET Rings,” International Conf. on Localization, Interaction, and Transport Phenomena in Impure Metals, Aug. 23-28, 1984; Braunschweig, FRG.Google Scholar
[13] Hu, E.L., Howard, R.E., “Reactive Ion Etching of GaAs in a Chlorine Plasma,” J. Vac. Sci. Technol., vol. B2, p. 85, (1984).CrossRefGoogle Scholar
[14] Tennant, D.M., “Metal on Polymer Ion Implantation Mask,” J. Vac. Sci. Technol., vol. B1, p. 494, (1983).CrossRefGoogle Scholar
[15] Howard, R.E., Jackel, L.D., Swartz, R.G., Grabbe, P., Archer, V.D., Epworth, R.W., Hu, E.L., Tennant, D.M., Voshchenkov, A.M., “Buried Channel MOSFETs with Gate Lengths from 2.5 μm to 700 Å,” IEEE Electron Dev. Lett., vol. EDL-3, 322, (1982).CrossRefGoogle Scholar
[16] Jackel, L.D., Swartz, R.G., Howard, R.E., Ko, P., Grabbe, P., “The CASFET: A MOSFET-JFET CASCODE Device with Ultra-Low Gate Capacitance,” IEEE Trans. Elect. Dev., To Appear.Google Scholar
[17] Skocpol, W.J., Jackel, L.D., Hu, E.L., Howard, R.E., Fetter, L.A., “One-Dimensional Locali-zation and Interaction Effects in Narrow (0.1μm) Silicon Inversion Layers,” Phys. Rev. Letters, vol.49, p. 951, (1982).Google Scholar
[18] Ralls, K.S., Skocpol, W.J., Jackel, L.D., Howard, R.E., Fetter, L.A., Epworth, R.W., Tennant, D.M., “Discrete Resistance Switching in Submicron Silicon Inversion Layers: Individual Interface Traps and Low-Frequency(/f')Noise,” Phys. Rev. Lett., vol.52, p. 228, (1984).Google Scholar
[19] Keyes, R.W., “Physical Limits in Digital Electronics,” Proc. IEEE, vol.63, p. 740, (1975).CrossRefGoogle Scholar