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CMP for Copper TSV Applications

Published online by Cambridge University Press:  01 February 2011

Max Gage
Affiliation:
Max_Gage@amat.com, Applied Materials, Inc., CMP Division, Silicon Systems Group, Sunnyvale, California, United States
Feng Liu
Affiliation:
Feng_Liu@amat.com, Applied Materials, Inc., CMP Division, Silicon Systems Group, Sunnyvale, California, United States
Kun Xu
Affiliation:
Kun_Xu@amat.com, Applied Materials, Inc., CMP Division, Silicon Systems Group, Sunnyvale, California, United States
You Wang
Affiliation:
You_Wang@amat.com, Applied Materials, Inc., CMP Division, Silicon Systems Group, Sunnyvale, California, United States
Yuchun Wang
Affiliation:
Yuchun_Wang@amat.com, Applied Materials, Inc., CMP Division, Silicon Systems Group, Sunnyvale, California, United States
Sherry Xia
Affiliation:
Sherry_Xia@amat.com, Applied Materials, Inc., CMP Division, Silicon Systems Group, Sunnyvale, California, United States
Wen-Chiang Tu
Affiliation:
Wen-Chiang_Tu@amat.com, Applied Materials, Inc., CMP Division, Silicon Systems Group, Sunnyvale, California, United States
Lakshmanan Karuppiah
Affiliation:
Lakshmanan_Karuppiah@amat.com, Applied Materials, Inc., CMP Division, Silicon Systems Group, Sunnyvale, California, United States
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Abstract

Through-silicon via (TSV) 3-D packaging and integration present many new opportunities and challenges for metals CMP applications. For front-side TSV polishing, challenges include the removal of large amounts of copper overburden, dishing control during copper clearing steps, and removal of large amounts of barrier metal and dielectric layers while still maintaining control over topography and defectivity. Additionally, the choice of barrier material can have significant impact on polishing in terms of the mechanical reliability regarding adhesion between the barrier metal and underlying dielectric layers. This paper will address many of these challenges with an emphasis on innovative technologies for superior process and endpoint controls, such as real-time profile control for thick copper films up to 6μm or more in thickness and automatic endpoint controls for barrier removal and dielectric stopping. The paper will also discuss some salient challenges for back-side TSV polishing, including the handling and polishing of bonded wafer pairs and strategies to minimize handling and polishing damage to the potentially fragile thinned device wafer. Additionally, the development of slurries with highly tunable copper-to-dielectric selectivity will be critical for enabling a wide range of final topographies, depending on requirements for subsequent bonding steps.

Keywords

Type
Research Article
Copyright
Copyright © Materials Research Society 2010

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References

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