Hostname: page-component-77c89778f8-rkxrd Total loading time: 0 Render date: 2024-07-20T08:27:14.556Z Has data issue: false hasContentIssue false
  • English
  • Français

An Assessment of Au Wire Bump Thermo-Mechanical Integrity in GaAs/Al2O3 Flip Chip Modules

Published online by Cambridge University Press:  15 February 2011

Jong-Kai Lin ,
Bennett Hileman ,
Russ Lee ,
Richard O'brien  and
Ravi Sharma
Jong-Kai Lin
Affiliation:
Motorola Inc., Semiconductor Products Sector, Advanced Packaging Development Center. MD: AZO1-B 136, 5005 E. McDowell Road, Phoenix, AZ 85008
Bennett Hileman
Affiliation:
Motorola Inc., Semiconductor Products Sector, Advanced Packaging Development Center. MD: AZO1-B 136, 5005 E. McDowell Road, Phoenix, AZ 85008
Russ Lee
Affiliation:
Motorola Inc., Semiconductor Products Sector, Advanced Packaging Development Center. MD: AZO1-B 136, 5005 E. McDowell Road, Phoenix, AZ 85008
Richard O'brien
Affiliation:
Motorola Inc., Semiconductor Products Sector, Advanced Packaging Development Center. MD: AZO1-B 136, 5005 E. McDowell Road, Phoenix, AZ 85008
Ravi Sharma
Affiliation:
Motorola Inc., Semiconductor Products Sector, Advanced Packaging Development Center. MD: AZO1-B 136, 5005 E. McDowell Road, Phoenix, AZ 85008
Get access

Abstract

The flexibility and cost advantages of the wire bumping process are making it increasingly attractive as an alternative bumping method for low I/O flip chip technologies. In this study, electrical measurements from DC to 8.1 GHz and die shear experiments are used to assess the thermo-mechanical integrity of Au/2%Pd wire bumped GaAs/Al2O3 flip chip modules. Finite Element Modeling results for in-process and in-service temperature cycling indicated that the maximum stress of the flip chip module is well below the failure stresses for GaAs, Al2O3 and the Au interconnect. These results are validated by data from thermal cycling experiments. Average shear strength after thermal cycle, thermal shock, and thermal aging (MIL-STD-883C, Condition C) was 64 grams/bump. Electrical characterization (from 45 MHz to 8.1 GHz) using a coplanar waveguide flip chip test structure showed no thermal stress-induced microwave energy losses.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 323: Symposium J – Electronic Packaging Materials Science VII , 1993 , 413
Copyright
Copyright © Materials Research Society 1994

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1. Scharr, T. A., Lee, R. T., Lytle, W. H., Subrahmanyan, R., and Sharma, R. K., Proceedings, 8th Electronic Materials and Processing Congress, San Jose, Aug.30 - Sep.2 (1993).Google Scholar
2. Scharr, T. A., Sharma, R. K., Lee, R. T., and Lytle, W. H., Proceedings, 9th ISHM European Hybrid Microelectronic Conference, Nice, France, June 2, 351–357 (1993).Google Scholar
3. Goodman, C. and Metroka, M., IEEE Trans. Comp. Hybrids Manuf. Technology., 15 (4), 457–464 (1992).CrossRefGoogle Scholar
4. Montgomery, C., Abstracts, VLSI and GaAs Packaging Workshop, Phoenix, Sept. (1991).Google Scholar
5. Reyes, A. and Dydyk, M., Motorola Technical Report #APDC-0193 (1993).Google Scholar
6. Subrahmanyan, R., Materials Research Symposium, Boston, Nov.29-Dec.3, #J9.2 (1993).Google Scholar
7. Sarihan, Vijay, Adhihetty, I. S., and Koehler, C.A., Proceedings, 8th Electronic Materials and Processing Congress, San Jose, Aug.30 - Sep.2 (1993).Google Scholar