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Stress-Induced Void Formation in Metal Lines

Published online by Cambridge University Press:  29 November 2013

Paul A. Flinn ,
Anne Sauter Mack ,
Paul R. Besser  and
Thomas N. Marieb
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Extract

The problem of stress-induced voiding in the metal lines used for VLSI interconnections appeared about 10 years ago and was first reported in the literature in 1984. Some typical voids are shown in Figure 1. It is not entirely coincidental that the problem is of about the same age as the personal computer. The continuing advances in process technology that make possible the ever lower costs and improved performance of VLSI devices often have unexpected and troublesome side effects. Continuous attention to potential effects of process changes on the behavior of the materials comprising a VLSI chip is essential to avoid passing on problems to customers. The history of stress-induced voiding provides a good illustration.

Type
Materials Reliability in Microelectronics
Information
MRS Bulletin , Volume 18 , Issue 12 , December 1993 , pp. 26 - 35
Copyright
Copyright © Materials Research Society 1993

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