In this work the electrical performance of a radiation hard designed 1T-1R resistive random access memory (RRAM) device is investigated in DC (voltage sweep) and AC (pulsed voltage) modes. This new device is based on the combination of an Enclosed Layout Transistor (ELT) used as selector device and a TiN/ HfO2/ Ti/TiN RRAM stack used as resistive device. The high cell to cell variability in the DC mode makes it difficult to define an electrical gap between the High Resistive State (HRS) and the Low Resistive State (LRS). The strong reduction of the variability by the use of Incremental Step Pulse with Verify Algorithm (ISPVA) makes the later a mandatory programming approach. The Quantum Point Contact (QPC) model defines an energy barrier located in the rupture point of the filament in HRS. The compensation between the width and height variations of this barrier during cycling could explain the stability of HRS and LRS. The good performance of the proposed device using the ISPVA programming approach makes it a good candidate for Rad-Hard Non Volatile Memories integration.