Skip to main content Accessibility help
×
Home

Bias Temperature Instability (BTI) in high-mobility channel devices with high-k dielectric stacks: SiGe, Ge, and InGaAs

  • J. Franco (a1), B. Kaczer (a1), A. Vais (a1) (a2), A. Alian (a1), H. Arimura (a1), V. Putcha (a1) (a2), S. Sioncke (a1), N. Waldron (a1), D. Zhou (a1), L. Nyns (a1), J. Mitard (a1), L. Witters (a1), M. Heyns (a1) (a2), G. Groeseneken (a1) (a2), N. Collaert (a1), D. Linten (a1) and A. Thean (a1)...

Abstract

We present a review of our recent studies of Bias Temperature Instability (BTI) in Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) fabricated with different material systems, highlighting the reliability opportunities and challenges of each novel device family. We discuss first the intrinsic reliability improvement offered by SiGe and Ge p-channel technologies, if a Si cap is used to passivate the channel, in order to fabricate a standard SiO2/HfO2 gate stack. We focus on SiGe gate stack optimizations for maximum BTI reliability, and on a simple physics-based model able to reproduce the experimental trends. This model framework is then used to understand the suboptimal BTI reliability and excessive time-dependent variability induced by oxide defect charging in different high-mobility channel gate stacks, such as Ge/GeOx/high-k and InGaAs/high-k. Finally we discuss how to pursue a reduction of charge trapping in alternative material systems in order to boost the device reliability and minimize time-dependent variability.

Copyright

Corresponding author

References

Hide All
1. Groeseneken, G., Degraeve, R., Kaczer, B., Martens, K., Trends and perspectives for electrical characterization and reliability assessment in advanced CMOS technologies , in IEEE Proc. Solid-State Device Research Conference (ESSDERC) 2010, pp.6473.
2. Asenov, A., Brown, A. R., Davies, J. H., Kaya, S., Slavcheva, G., Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs , in IEEE Transactions on Electron Devices, Vol. 50, No. 9, pp. 18371852 (2003).
3. Grasser, T., Kaczer, B., Goes, W., Reisinger, H., Aichinger, T. et al., The Paradigm Shift in Understanding the Bias Temperature Instability: from Reaction-Diffusion to Switching Oxide Traps , in IEEE Transactions on Electron Devices, Vol. 58, No. 11, pp. 36523666 (2011).
4. Kaczer, B., Grasser, T., Roussel, P., Franco, J., Degraeve, R. et al., Origin of NBTI variability in deeply scaled pFETs ,, in IEEE Proc. International Reliability Physics Symposium (IRPS) 2010, pp. 2632.
5. Kuhn, K. J., Considerations for Ultimate CMOS Scaling , in IEEE Transactions on Electron Devices, Vol. 59, No. 7, pp. 18131828 (2012).
6. Franco, J., Kaczer, B., Stesmans, A., Afanas’ev, V., Martens, K. et al. , Impact of Si-Passivation Thickness and Processing on NBTI Reliability of Ge and SiGe p-MOSFETs , presented at the 2009 IEEE Semiconductor Interface Specialists Conference (SISC), Arlington, VA, 2009 (unpublished).
7. Franco, J., Kaczer, B., Cho, M., Eneman, G., Groeseneken, G. et al. , Improvements of NBTI reliability in SiGe p-FETs , in IEEE Proc. International Reliability Physics Symposium (IRPS) 2010, pp. 10821085.
8. Franco, J., Kaczer, B., Eneman, G., Mitard, J., Stesmans, A. et al., 6Å EOT Si 0.45 Ge 0.55 pMOSFET with Optimized Reliability (V DD =1V): Meeting the NBTI Lifetime Target at Ultra-Thin EOT , in IEEE Proc. International Electron Devices Meeting (IEDM) 2010, pp. 7073.
9. Franco, J., Kaczer, B., Roussel, P., Mitard, J., Cho, M. et al., SiGe channel technology: Superior reliability toward ultrathin EOT devices; part I: NBTI , in IEEE Transactions on Electron Devices, vol. 60, pp. 396404 (2013).
10. Krishnan, S., Kwon, U., Moumen, N., Stoker, M., Harley, E. et al. , A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications , in IEEE Proc. International Electron Devices Meeting (IEDM) 2011, pp. 634637.
11. Gong, X., Su, S., Liu, Bin, Wang, L., Wang, Wei et al. , Fabrication and Negative Bias Temperature Instability (NBTI) Study on Ge 0.97 Sn 0.03 p-MOSFETs with Si 2 H 6 Passivation and HfO 2 High-k and TaN Metal Gate , in Electrochemical Society Transactions, Vol. 50, No. 9, pp. 949956 (2012).
12. Franco, J., Kaczer, B., Toledano-Luque, M., Roussel, Ph. J., Kauerauf, T. et al. , SiGe Channel Technology: Superior Reliability toward Ultra-Thin EOT devices–Part II: Time-Dependent Variability in Nanoscaled Devices and Other Reliability Issues , in IEEE Transactions on Electron Devices, Vol. 60, No. 1, pp. 405412 (2013).
13. Franco, J., Kaczer, B., Roussel, P., Mitard, J., Sioncke, S. et al., Understanding the suppressed charge trapping in relaxed- and strained-Ge/SiO 2 /HfO 2 pMOSFETs and implications for the screening of alternative high-mobility substrate/dielectric CMOS gate stacks , in IEEE Proc. International Electron Devices Meeting (IEDM) 2013, pp. 15.2.1-4.
14. Martens, K., Mitard, J., De Jaeger, B., Meuris, M., Maes, H. et al. , Impact of Si-thickness on interface and device properties for Si-passivated Ge pMOSFETs , in IEEE Proc. Solid-State Device Research Conference (ESSDERC) 2008, pp. 138141.
15. Zhang, R., Taoka, N., Huang, P., Takenaka, M. and Takagi, S., 1-nm-thick EOT high mobility Ge n- and p-MOSFETs with ultrathin GeOx/Ge MOS interfaces fabricated by plasma post oxidation , in IEEE Proc. International Electron Device Meeting (IEDM) 2011, pp. 642645.
16. Alian, A., Pourghaderi, M.A., Mols, Y., Cantoro, M., Ivanov, T., et al. , Impact of the channel thickness on the performance of ultrathin InGaAs channel MOSFET devices , in IEEE Proc. International Electron Device Meeting (IEDM) 2013, pp. 16.6.1-4.
17. Franco, J. Alian, A., Kaczer, B., Lin, D., Ivanov, T. et al. , Suitability of high-k gate oxides for III–V devices: A PBTI study in In 0.53 Ga 0.47 As devices with Al 2 O 3 , in IEEE Proc. International Reliability Physics Symposium (IRPS) 2014, pp. 6A.2.1-4.
18. Franco, J., Kaczer, B., Waldron, N., Roussel, Ph.J., Alian, A. et al., RTN and PBTI-induced Time-Dependent Variability of Replacement Metal-Gate High-k InGaAs FinFETs , in IEEE Proc. International Electron Device Meeting (IEDM) 2014, pp. 506509.

Keywords

Related content

Powered by UNSILO

Bias Temperature Instability (BTI) in high-mobility channel devices with high-k dielectric stacks: SiGe, Ge, and InGaAs

  • J. Franco (a1), B. Kaczer (a1), A. Vais (a1) (a2), A. Alian (a1), H. Arimura (a1), V. Putcha (a1) (a2), S. Sioncke (a1), N. Waldron (a1), D. Zhou (a1), L. Nyns (a1), J. Mitard (a1), L. Witters (a1), M. Heyns (a1) (a2), G. Groeseneken (a1) (a2), N. Collaert (a1), D. Linten (a1) and A. Thean (a1)...

Metrics

Full text views

Total number of HTML views: 0
Total number of PDF views: 0 *
Loading metrics...

Abstract views

Total abstract views: 0 *
Loading metrics...

* Views captured on Cambridge Core between <date>. This data will be updated every 24 hours.

Usage data cannot currently be displayed.