Hostname: page-component-76fb5796d-2lccl Total loading time: 0 Render date: 2024-04-27T01:51:25.728Z Has data issue: false hasContentIssue false

Succeeded Foundation Effect of Stretched Gate and SiGe Array Diffusion Zones on Film-Type Strained Silicon pMOSFETs

Published online by Cambridge University Press:  26 February 2018

C. C. Lee*
Affiliation:
Department of Power Mechanical EngineeringNational Tsing Hua UniversityHsinchu, Taiwan
C. P. Hsieh
Affiliation:
Department of Mechanical EngineeringNational Taiwan UniversityTaipei, Taiwan
*
*Corresponding author (cclee@pme.nthu.edu.tw)
Get access

Abstract

It has demonstrated to exploit various layout effects of advanced strained engineering to enhanced the performance of nano-scaled transistors. In actual fabrications, the gate framework usually protrudes out to the channel area even over the spuriously diffused active region, over the soft shallow trench isolation region. The foregoing device feature is interesting and critical when enhancing and managing mobility gain are taken into account by used mechanics and induced strained silicon technology in narrow scale channel widths devices. Thus, a silicon-based 22 nm p-type MOSFET combined stressors of a source/drain Si75Ge25 alloy and a -2 GPa compressive contact etch stop layer with different protrudent gate widths to investigate this issue. The fabricated oriented stress simulation extracted stress component within the device channel to estimate and analyze the performance of mobility gain and stress contours for the concerned nanoscale device.

Type
Research Article
Copyright
Copyright © The Society of Theoretical and Applied Mechanics 2018 

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1. Ito, S. et al., “Mechanical Stress Effect of Etch-Stop Nitride and Its Impact on Deep Submicron Transistor Design,” IEEE Electron Devices Meeting, pp. 247250 (2000).Google Scholar
2. Adams, V. et al., “1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations,” IEEE Symp VLSI Technology Dig, pp. 6263 (2006).Google Scholar
3. Oberhuber, R. et al., “Mobility Enhancement of Two-Dimensional Holes in Strained Si/SiGe MOSFETs,” Solid-State Device Research Conference, pp. 524527 (1998).Google Scholar
4. Lee, C. F. et al., “Strain Engineering for Electron Mobility Enhancement of Strained Ge NMOSFET with SiGe Alloy Source/Drain Stressor,” Microelectronic Engineering, 138, pp. 1216 (2015).Google Scholar
5. Moriyama, Y. et al., “Introduction of Local Tensile Strain on Ge Substrates by SiGe Stressors Selectively Grown on Wet Chemically Recessed Regions for Strained Ge-nMOSFETs,” Solid-State Electron, 60, pp. 8992 (2011).Google Scholar
6. Kobayashi, M. et al., “Uniaxial Stress Engineering for High-Performance Ge NMOSFETs,” IEEE Transactions on Electron Devices, 57 pp. 10371046 (2010).Google Scholar
7. Zhang, D. et al., “Embedded SiGe S/D PMOS on Thin Body SOI Substrate with Drive Current Enhancement,” IEEE Symposium on VLSI Technology, pp. 2627 (2005).Google Scholar
8. Mizuno, T. et al., “Advanced SOI-MOSFETs with Strained-Si Channel for High Speed CMOS-Electron/ Hole Mobility Enhancement,” IEEE Symposium on VLSI Technology, pp. 210211 (2000).Google Scholar
9. Wang, G. H. et al., “Silicon-Germanium-Tin (SiGeSn) Source and Drain Stressors Formed by Sn Implant and Laser Annealing for Strained Silicon-Germanium Channel P-MOSFETs,” IEEE International Electron Devices Meeting, pp. 131134 (2007).Google Scholar
10. Sheraw, C. D. et al., “Dual Stress Liner Enhancement in Hybrid Orientation Technology,” IEEE Symposium on VLSI Technology, pp. 1213 (2005).Google Scholar
11. Shin, K. et al., “Effect of Tensile Capping Layer on 3-D Stress Profiles in FinFET Channels,” Device Research Conference Digest, pp. 201202 (2005).Google Scholar
12. Smith, L. et al., “Exploring the Limits of Stress-Enhanced Hole Mobility,” IEEE Electron Device Letters, 26, pp. 652654 (2005).Google Scholar
13. Sugii, N. et al., “Enhanced Performance of Strained Strained-Si MOSFETs on CMP Sige Virtual Substrate,” IEEE International Electron Devices Meeting, pp. 737740 (2001).Google Scholar
14. Mizuno, T. et al., “High Performance Strained-Si p-MOSFETs on SiGe-on-Insulator Substrates Fabricated by SIMOX Technology,” IEEE International Electron Devices Meeting, pp. 934936 (1999).Google Scholar
15. Nayak, D. K. et al., “High-Mobility Strained-Si PMOSFET's,” IEEE Transactions on Electron Devices, 43, pp. 17091716 (2002).Google Scholar
16. Su, Y.-F. et al., “Design and Reliability Assessment of Novel 3D-IC Packaging,” Journal of Mechanics, 33, pp. 193203 (2017).Google Scholar
17. Lee, C. H. et al., “A Novel Acceleration-Factor Equation for Packaging-Solder Joint Reliability Assessment at Different Thermal Cyclic Loading Rates,” Journal of Mechanics, 33, pp. 3540 (2017).Google Scholar
18. Smith, C. S., “Piezoresistance Effect in Germanium and Silicon,” Physical Review Letters, 94 pp. 4249 (1954).Google Scholar