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Application of Line Modified-Asymmetric Crystal Topography for Qualitative and Quantitative Evaluation of Integrated Circuits

  • K. A. Green (a1), W. T. Beard (a2), X. J. Zhang (a1) and R. W. Armstrong (a1)


X-ray diffraction topography is the name given to several x-ray diffraction techniques where large area x-ray beams diffracted from a crystal provide detailed information about the surface structure and internal perfection of crystal microstructures. Since x-ray topographic techniques are based on Bragg (reflection) or Laue (transmission) diffraction from a crystal lattice, they are extremely sensitive to any atomic lattice imperfections and strains. Alterations of the interplanar spacing as small as one part in ten thousand extending over a reasonable number of atomic ce11 lengths can be recorded as a corresponding change in the diffracted beam intensity. Line Modified-Asymmetric Crystal Topography (LM-ACT) is one such reflection technique that shows particular promise in Che field of microelectronics. The LM-ACT system is designed with low angular divergence in the x-ray beam probe. Low probe beam divergence allows details of device geometries on the order of microns to be resolved in the recorded x-ray intensity variation of the diffracted beam.

The LM-ACT system was applied here to the study of integrated circuits (IC) after specific processing steps were accomplished during IC fabrication and in the final product condition. Topographs obtained from specular crystal surfaces that were implanted through a patterned mask showed contrast variations between the implanted and non-implanted regions; details of the mask patterns have been resolved on the order of a few microns. LMACT topographs from annealed, and unannealed, Implanted specimens showed marked differences and as a result it is suggested that LM-ACT would be beneficial in optimizing the processing schedule for a particular wafer/electronic system. A significant feature of the LM-ACT technique is the capability for producing high resolution stereo-pair topographs that provide quantitative information through the depth of individual process layers in an integrated circuit.



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