The traditional geometrical scaling of the CMOS technologies has recently evolved in a generalized scaling scenario where material innovations for different intrinsic regions of MOS transistors as well as new device architectures are considered as the main routes toward further performance improvements. In this regard, high-κ dielectrics are used to reduce the gate leakage with respect to the SiO2 for a given drive capacitance, while the on-current of the MOS transistors is improved by using strained silicon and possibly with the introduction of alternative channel materials. Moreover, the ultra-thin body Silicon-On-Insulator (SOI) device architecture shows an excellent scalability even with a very lightly doped silicon film, while non-planar FinFETs are also of particular interest, because they are a viable way to obtain double-gate SOI MOSFETs and to realize in the same fabrication process n-MOS and p-MOS devices with different crystal orientations.

Given the large number of technology options, physically based device simulations will play an important role in indicating the most promising strategies for forthcoming CMOS technologies. In particular, most of the device architecture and material options discussed above are expected to affect the performance of the transistors through the band structure and the scattering rates of the carriers in the device channel. Hence microscopic modeling is necessary in order to gain a physical insight and develop a quantitative description of the carrier transport in advanced CMOS technologies.

In this context, our book illustrates semi-classical transport modeling for both n-MOS and p-MOS transistors, extending from the theoretical foundations to the challenges and opportunities related to the most recent developments in nanometric CMOS technologies.