Introduction

In previous chapters, we have discussed the importance of capturing the transistor performance as a function of temperature and the changes that occur to the material parameters. While it is necessary to characterize and model this behaviour, transistors designed for high power densities also generate heat as a by-product of current flow within the junction area. This self-heating degrades the performance of the transistor and these effects must be included within our models.

To quantify the amount of self-heating we need only look at the definition of power-added efficiency η, (Pout − Pin)/Pdc, where Pin and Pout are the input and output power at the operational frequency of the transistor, respectively, and Pdc is the supplied DC power. Power that is not converted from DC to RF or is transferred into the device, approximately Pdc(1 − η), is dissipated as heat. The vast amount of generated heat flows away from the junction into the bulk semiconductor, down into the package flange, and then into the heatsink of the power amplifier. Maximum junction temperatures for transistors used within wireless base-stations are often specified to be around 150–200°C, depending on the device technology in use.

High-power transistors are operated close to the maximum limits of their electrical and thermal specifications, to extract the best possible device performance as economically as possible, in other words, to produce the maximum RF power per dollar of expenditure [1].