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Short-channel Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs) often utilize T-shape gates due to their large gate-line cross-sectional area and subsequent fMAX increase. In this paper, we report the linearity trade-offs associated with varying the T-gate geometries of AlGaN/GaN HEMTs on Si, specifically the gate extensions which serve as field plates and their impact on the large-signal performance. Small-signal characterization and modeling, in addition to TCAD, provide initial guidelines for the optimal dimensions for the gate field plates using the ratio of fT and the product of the gate resistance and the gate-to-drain capacitance. We utilize various characterization methods, including 6 GHz non-linear vector network analyzer characterization in addition to load-pull, to quantify the amplitude and phase distortion and their subsequent impact on the large-signal metrics of the devices under differing matching conditions and bias points. We deduce that the influence of the gate field plates on the amplitude and phase distortion is non-negligible, particularly under matched conditions.
Current semiconductor devices have been scaled to such dimensions that we need take an atomistic approach to understand their characteristics. The atomistic nature of these devices provides us with a tool to study the physics of very small ensembles of dopants right up to the limit of a single atom. Control and understanding of a dopants wavefunction and its coupling to the environment in a nanostructure could proof a key ingredient for device technology beyond-CMOS. Here, we will discuss the eigenlevels and transport characteristics a single gated As donor. The donor is incorporated in the channel of wrap-around gate transistors (FinFETs). The measured level spectrum is shown to consist of levels associated with the donors Coulomb potential, levels associated with a triangular well at the gate interface and hybridized combinations of the two. The level spectrum of this system can be well described by a NEMO-3D model, which is based on a numerical tight-binding approximation.
FinFET is one of the leading candidates to replace the classical planar MOSFET for future CMOS technologies due to the double-gate configuration of the device leading to an intrinsically superior short channel effect (SCE) control. A major challenge for FinFETs is the increase in parasitic source-drain resistance (Rsd) as the fin width is scaled. As fins must be narrow in order to control SCEs, Rsd reduction is critical. This work will deal with the challenges faced in the use of ion implantation for the low-ohmic source-drain contacts. Firstly a new technique to characterize fin sidewall doping concentration will be introduced. We will have a closer look at the Rsd dependency upon fin width for different fin implant conditions and investigate how the implant conditions affect FinFET device performance. It will be shown that the cause of the device degradation upon fin width scaling is related to the fundamental issues of silicon crystal integrity in thin-body Si after amorphizing implant and recrystallization during source-drain activation.
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