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The need for high-κ gate dielectrics and metal gates in advanced integrated circuits has reopened the door to Ge and III–V compounds as potential replacements for silicon channels, offering the possibility to further increase the performances of complementary metal oxide semiconductor (CMOS) circuits, as well as adding new functionalities. Yet, a fundamental issue related to high-mobility channels in CMOS circuits is the electrical passivation of their interfaces (i.e., achieving a low density of interface defects) approaching state-of-the-art Si-based devices. Here we discuss promising approaches for the passivation of Ge and III–V compounds and highlight insights obtained by combining experimental characterization techniques with first-principles simulations.
High-grade basic and acidic meta-igneous rocks are widespread in the bimodal amphibolitic—felsic gneiss complexes, which are characteristic formations of the ‘Middle Allochthonous Unit’ from eastern and southern French Massif Central. The metabasites from the Lyonnais and Doux complexes are chemically diverse and range from N-MORB type tholeiitic to transitional types. The two populations are not related by fractional crystallization or crustal contamination processes and their chemical characteristics reflect differences in their mantle sources. An ensialic setting is supported by the crustally-derived character of some of the associated felsic rocks, but the presence of N-MORB-type metabasites argues for an extensional environment. This bimodal association compares well with the magmatism of rifted continental margins and may reflect a transitional stage between continental rifting and oceanic crust formation during the Cambro-Ordovician spreading event.
High mobility channel materials and new device structures will be needed to meet the power and performance specifications in future technology nodes. Therefore, the use of Ge and III/V materials and novel devices such as heterojunction TunnelFET’s is investigated for future CMOS applications. High-performance CMOS can be obtained by combining Ge pMOS devices with nMOS devices made on III/V compounds such as InGaAs. In all cases the key challenge is the electrical passivation of the interface between the high-k dielectric and the alternative channel materials.
Recent studies have demonstrated good electrical properties of the GeO2/Ge interface. Since the GeO2 layer is very hygroscopic, full in-situ processing of GeO2 formation and high-k deposition must be performed or other methods must be employed to stabilize the GeO2 layer. One of the most successful passivation techniques for Ge MOS gate stacks is a thin, epitaxial layer of Si. A lot of attention went into better understanding of this passivation and the effects of its optimization on various device characteristics. It was found that mobility and Vt trends in both pMOS and nMOS transistors can be explained based on defects located at the Si/SiO2 interface.
Unfortunately, III-V/oxide interfaces are not quite as robust and most interfaces present rather high densities of interface states. Although, considerable improvements have been realized in the reduction of the interface state density, further developments are required to obtain high performance MOS devices. To this purpose various passivation methods were critically evaluated. Simulations using Density Functional Theory reveal the possibility of using a thin amorphous layer made of GeOX to obtain an electrically unpinned gap. The major challenge resides in the control of the c-Ge thickness and the oxidation of this layer to avoid the diffusion of oxygen atoms at the Ge/GaAs(001) interface. Promising results are obtained by optimizing the surface preparation, high-k deposition and annealing cycle on In0.53Ga0.47As-Al2O3 interfaces. Self-aligned inversion channel n-MOSFETs fabricated on p-type In0.53Ga0.47As demonstrate inversion-mode operation with high drive current and a peak electron mobility of 3000 cm2/Vs.
Since ultimately the major showstopper on the scaling roadmap is not device speed, but rather power density, the introduction of these advanced materials will have to go together with the introduction of new device concepts. Novel structures such as heterojunction TunnelFET’s can fully exploit the properties of these new materials and provide superior performance at lower power consumption by virtue of their improved subthreshold behaviour. Vertical surround gate devices produced from nanowires allow the introduction of a wide range of materials on Si. This illustrates the possibilities that are created by the combination of new materials and devices to allow scaling of nanoelectronics beyond the Si roadmap.
Future CMOS technologies will require the use of substrate material with a very high mobility. Therefore, the combination of Ge pMOS with GaAs nMOS devices is investigated for its possible use in advanced CMOS applications. In this work, the physical, chemical and electrical properties of a-GeO2 interfacial passivation layer (IPL) for n-Ge(001) and p-GaAs(001) have been investigated, using Molecular Beam Epitaxy (MBE) technique. The efficient electrical passivation of Ge/GeO2 will be demonstrated, and in the case of GaAs, the use of a thin a-GeO2 interlayer reduces the defects at the interface.
We present a one-dimensional simulation study of the capacitance-voltage (C-V) and current-voltage (I-V) characteristics in MOS devices with high mobility semiconductors (Ge and III-V materials) and non-conventional gate stack with high-κ dielectrics. The C-V quantum simulation code self-consistently solves the Schrödinger and Poisson equations and the electron transport through the gate stack is computed using the non-equilibrium Green’s function formalism (NEGF). Simulated C-V characteristics are successfully confronted to experimental data for various MOS structures with different semiconductors and dielectric stacks. Simulation of I-V characteristics reveals that gate leakage current strongly depends on gate stacks and substrate materials and predicts low leakage current for future CMOS devices with high mobility materials and high-κ dielectrics.
The time-dependent dielectric breakdown of MOS capacitors with ultra-thin gate oxide layers is investigated. After the occurrence of soft breakdown, the gate current increases by 3 to 4 orders of magnitudes and behaves like a power law of the applied gate voltage. It is shown that this behavior can be explained by assuming that a percolation path is formed between the electron traps generated in the gate oxide layer during electrical stress of the capacitors. The time dependence of the gate voltage signal after soft breakdown is next analysed. It is shown that the fluctuations in the gate voltage are non-gaussian as well as that long-range correlations exist in the system after soft breakdown. These results can be explained by a dynamic percolation model, taking into account the trapping-detrapping of charges within the percolation cluster formed at soft breakdown.
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