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Critical dimension (CD) shrink and patterning of contact features via plasma etching were studied for typical resistive random access memory (RRAM) stacks. These consist of SiO2 and Si3N4 (total thickness of 65 80 nm) with NiO or pure Ni at the bottom. First, the contact patterning of RRAM stacks was investigated for 90 nm contacts. Thus, a standard high power contact etch recipe was shown to give rise to resist strip challenges due to the incorporation of sputtered Ni in the resist film. Therefore, a low-sputter-yield contact etch recipe based on a CF4/H2/Ar gas chemistry was introduced. The ion sputter efficiency of the recipe was estimated from a blanket SiO2 sputter-yield experiment in Ar plasma for the same recipe settings: this yielded values close to the Ni sputter-yield threshold. Second, plasma-assisted CD shrink was studied in combination with the newly developed patterning scheme to get the contact CD well below the initial 90-nm litho print size. It was shown that a low contact etch power regime could also provide a larger window for contact CD shrink using a C2H4-based chemistry: e.g. the demonstrated CD shrink from 90 nm down to sub-40 nm was shown to be extremely challenging in the case of a high power regime due to polymer instability enhanced with the resulting thickness increase. Perhaps, the relaxation of the polymer film stress, which was measured to be in the range of 1200-1500 MPa, is more easily triggered at higher power settings, which leads to polymer blistering. Finally, the optimization of the plasma-assisted CD shrink step in combination with the low-sputter-yield contact etch recipe was demonstrated to be able to provide CDs as small as 27 nm. The demonstrated approach shows that plasma-assisted CD shrink can provide a robust test vehicle for research programs that require the patterning of small features in the sub-40-nm CD range.
FinFET is one of the leading candidates to replace the classical planar MOSFET for future CMOS technologies due to the double-gate configuration of the device leading to an intrinsically superior short channel effect (SCE) control. A major challenge for FinFETs is the increase in parasitic source-drain resistance (Rsd) as the fin width is scaled. As fins must be narrow in order to control SCEs, Rsd reduction is critical. This work will deal with the challenges faced in the use of ion implantation for the low-ohmic source-drain contacts. Firstly a new technique to characterize fin sidewall doping concentration will be introduced. We will have a closer look at the Rsd dependency upon fin width for different fin implant conditions and investigate how the implant conditions affect FinFET device performance. It will be shown that the cause of the device degradation upon fin width scaling is related to the fundamental issues of silicon crystal integrity in thin-body Si after amorphizing implant and recrystallization during source-drain activation.
Junction formation in FinFET-based 3D-devices is a challenging problem as one targets a complete conformal doping of the source/drain regions in order to produce equal gate-profile overlaps (and thus transistor behavior) on all sides of the fins. Due to the lack of predictive modeling for several of the doping strategies explored (plasma immersion, cluster implants, vapor phase deposition, etc…) it becomes difficult to correctly predict the performance of the devices and hence, accurate 3D-doping profile determination is desired. Although several dopant/carrier profiling methods exist with excellent one- or two-dimensional resolution and properties, there is an urgent need to extend these towards a quantitative three-dimensional geometry. In this work, we use scanning spreading resistance microscopy (SSRM) with dedicated FinFET test structure to obtain three-dimensional information from successive two-dimensional scanning spreading resistance maps. We also assess the validity of our methodology by comparing various sections along the fins which represent the variability due to the processing and measurement procedure.
The electrical and material characterization of Ti(C)N deposited by metal organic chemical vapor deposition (MOCVD) technique, as metal gate electrode for advanced CMOS technology is investigated. The effects of the plasma treatment, post anneal treatment and the thickness variation of the Ti(C)N film on the flat band voltage (VFB) and effective work function (WF) of the Poly-Si/Ti(C)N/SiO2 Poly-Si/Ti(C)N/SiO2 gate stack s are reported. We found that both the in-situ plasma treatment and post anneal treatment help in reducing the carbon content (organic) in the film making it more metallic compared to the as-deposited films. However, the post anneal treatment was found to be a better option for getting rid of hydrocarbons as compared to plasma treatment from the gate dielectric integrity point of view. The thickness variation of post annealed Ti(C)N film ranged from 2.5 nm to 10 nm lead to WF shift of upto ~350 mV for both Poly-Si/Ti(C)N/SiO2 and Poly-Si/Ti(C)N/HfO2 gate stacks.
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