The explosive growth under way in the performance of digital electronic
systems is directly traceable to the impact of Si MOS device scaling and its
accompanying increase in functionality at the chip level. The increasing
data rates and chip I/O that have accompanied this scaling have driven the
evolution of both system architectures and the interconnection and packaging
technologies (i.e. chip carriers, printed circuit boards, bus structures)
that support this CMOS functionality and dominate overall system volume. The
further scaling of CMOS technology towards 0.1 – 2.5μm
minimum gate lengths coupled with modest increases in chip size (i.e. 2–4
cm), promise upwards of a 100 fold increase in chip-level complexity. The
resulting emergence of Ultra Large Scale Integrated (ULSI) processor array
chips and wafer-scale memory (solid state disks) hold the potential for
extremely compact distributed computing systems. Through a continuation of
the evolutionary trends of system scaling, application of chip level process
technology to higher system levels, and mixed technology integration (e.g.
BiCMOS); present advanced packaging technologies based upon Multi-Chip
Modules (MCM) will mature into hybrid wafer-level three-dimensional silicon
systems allowing burdensome driver and communication control functions now
designed at the chip level to move off chip into the active silicon
interconnection substrate where network transmission and control can both be
implemented. Realization of the performance potential of these silicon ULSI
systems will largely depend on the successful implementation of this
wafer-level communication network linking the high-density of processing
nodes. The role that any advanced technology (i.e. high-speed normal
electronic, superconducting, optical) will serve within this network will be
determined by the degree of connectivity it can achieve in this scaled
environment and by its ability to benignly coexist with the dominant CMOS
technology, the network's physical and functional foundation[l].