A novel oxynitride processing scheme has been developed to provide improved performance over thermal oxides. These dielectrics were formed by nitridation of bare silicon wafers followed by deposition of low pressure chemical vapor deposited (LPCVD) oxides at 450°C and reoxidation at 900°C. This novel process provides a good control of dielectric thickness and the amount of nitrogen incorporated at the silicon/silicon dioxide interface. It also reduces the incorporation of the hydrogen-related electron traps in the bulk of the dielectric. Excessive electron trapping is a potential problem of the nitrided oxides. These oxynitride dielectrics referred to as “LPCVD Oxynitride” or “Reoxidized CVD Oxide on Nitrided Silicon” also exhibit relatively large charge-to-breakdown (QBD), considerable reduction in electron trapping and interface state (Dit) generation. The dielectric integrity of these LPCVD Oxynitride was also compared to other oxynitrides which were formed by oxidation of nitrided silicon (“Oxidized-Nitrided Silicon Dielectric”). It was found that the electrical characteristics of the oxidized nitrided silicon dielectrics are inferior compared to the LPCVD oxynitrides (e.g., QBD is substantially lower). Furthermore, for the case of LPCVD oxynitrides, higher nitridation temperatures leads to larger QBD. These results might be explained by the model in which microdefects are incorporated into the oxide when the silicon is consumed as in the cases of oxidized-nitrided silicon dielectrics.

The effect of high temperature annealing, in the temperature range of 600∼900°C on the electrical properties and microstructure of tantalum pentoxide (Ta2O5) film deposited by PECVD was studied. The leakage current of the Ta2O5 film annealed at 600°C showed a minimum value in this study. However, it was found that the leakage current in the polycrystalline Ta2O5 film annealed above 800°C was decreased by increasing the annealing temperature. The dielectric constant of the annealed Ta2O5 film was 26 at 600°C, and decreased with the same tendency as leakage current characteristics. TEM and XRD analysis indicated that the microstructure of the Ta2O5 film annealed above 800°C was of ε-Ta2O5 with hexagonal crystal structure. Furthermore, TEM and AES observations revealed that Ta-O-Si transition layers were formed between annealed Ta2O5 layer and Si substrate. The electrical properties of the Ta2O5 films were discussed in terms of interface modification and film densification due to post-annealing

We report, for the first time, on interface properties of the Ta2O5-Si system and on the deep level defects in Ta2O5 grown by plasma enhanced liquid source chemical vapor deposition (PE-LS-CVD) using Ta(OC2Hs)5. The capacitance voltage (C–V) measurement performed on Au/Ta2O5/n, p-Si MOS diodes resulted in very well defined C-V charactristics which compares well with the ideal C-V curve. The flat band voltage is as low as 0.15 V and the minimum density of the interface state is about 2.7 × 1011 cm−2 ev−1. In order to examine deep level defects in Ta2O5, we investigated variations of flat band voltage under application of high stress electric field (10MV/cm), by which hot carriers are injected in to deep levels. This charge transfer process results in increase of charges in Ta2O5 oxide which is attributed to the equivalent deep level defect densities, which is found to be of the order of 2 × 1011 cm−2 in the Ta2O5-Si system. These results strongly suggest low interface states and deep levels in the PE-LS-CVD grown Ta2O5-Si system, which may be brought about by low decomposed-carbon impurities in the film, confirmed by AES in our previous reports. These films can play a vital role as thin capacitors in I.C. technology.

Peeling of flexible poly(ethylene terephthalate), PET, and elastic steel films, adhesively bonded with a pressure sensitive adhesive layer, was analyzed from a thermodynamic perspective with the intent of determining how the energy expended in separating the bonded materials is consumed. The mechanical work expended and the heat dissipated during peeling were simultaneously measured using deformation calorimetry. For the PET backing material, which has a demonstrated capacity to store deformation energy as latent internal energy, most, but not all, of the peel energy was dissipated as heat. When perfectly elastic steel films were peeled, all of the peel energy was dissipated as heat, proving that no latent internal energy is stored in the adhesive layer during peeling and suggesting that the internal energy change of peeling adhesive backed with PET film was stored as latent internal energy in the PET backing. The stored latent internal energy in the peeled PET was measured using solution calorimetry. The thermodynamics of tensile drawing for PET was studied using deformation calorimetry, solution calorimetry, differential scanning calorimetry and thermomechanical analysis.

Using a new, high resolution, microscopic Scanning Kelvin Probe (SKP), work function topographies of metal, semiconductor and metal/semionductor surfaces have been studied in both Ultra-High-Vacuum (UHV) and air environments.

The work function is a very sensitive indicator of surface and Interface condition and has been previously utilized to examine preparation methods, surface roughness, adsorption processes, thin film monitoring and residual surface contamination.

Extension of the basic method, via Illumination of the semiconductor surface under the tip allows one to probe the local density of states (LDOS). Variations in LDOS can be used to monitor metal contamination, interface traps, bulk contamination, oxide imperfections, etc.

Work function topographies generated in this fashion have application in quality control at all stages of the manufacturing process. The Kelvin method of measuring work function is non-contact and non-destructive, utilizing neither high fields nor large currents. It can be applied to a variety of environments ranging from UHV to air and at a wide range of temperatures.

Chemically vapor deposited phosphosilicate glass (PSG) has been used extensively for final passivation on EPROM and other Non Volatile Memory (NVM) technologies. The maximum amount of phosphorous that can be added to the passivation oxide (post metallization) is constrained by the stability of the as-deposited, undensified film. Atmosphericpressure chemically vapor deposited films of various dopant levels ranging from pure PSG to various boron and phosphorous wt%BPSG films were studied with respect to their passivation properties. The film performance with respect to passivation crack resistance, step coverage, and impacts on metal cracks/voids was evaluated. It was found that the crack resistance was by far more sensitive to boron concentration than that of phosphorous in the undensified film. The crack resistance is shown to be dependent on the as-deposited film densities, moisture levels and amount of shrinkage after a 400° C alloy/anneal. Other important parameters such as stress levels, UV transparency and sodium gettering capabilities were investigated. Reliability data on packaged-device level testing (both ceramic and plastic units) are also presented.

A non destructive method to characterize the properties of SiO2 films in SiO2-Si structures and analyze their variations under different external actions is presented and discussed. The method is based on the properties of the Electrolyte-SiO2 contact under polarization which allows us to study the SiO2 film in different injection conditions, in a hole injection zone, in a predominant electron injection zone, and finally, in a region of electron heating as a result of the electric field action before to reach the oxide breakdown. Moreover, using this method, higher electric field values than in the metal-SiO2-Si system can be applied.

The characterization of hole traps, electron traps and defect precursors states in SiO2 films are carried out as well as their evolution and influence on the SiO2-Si structure degradation and electrical behaviour. Results measured on SiO2-Si structures obtained from different technological processes and submitted to different treatments are reported in order to discuss the possibilities of this method as a power tool to assess the stability and quality of insulating layer on semiconductors.

The damage of films of two different passivation materials deposited on aluminium substrates was investigated. These systems were subjected to uniaxial stretch in an in situ tensile testing device adapted to a scanning electron microscope. Successive stages of crack development were observed: the failure is first in the film, then at the interface. The presence of a thermally grown aluminium oxide interlayer delays the decohesion process. The substrate surface roughness weakens the systems. The evolution of the crack density with the longitudinal strain was analysed and then fitted with a model based on a Weibull distribution function.

In this study, possible SiO2 damage that could result from several different photoresist ashing techniques has been assessed using patterned photoresist over blanket oxides. The types of ashing systems used were RF power (RF), upstream ozone generator (Upstream) and two microwave power reactors (Microwave 1 and Microwave 2). Aluminum capacitors were evaporated on the samples after the ashing for oxide evaluation. Electrical characterization of these MOS structures included capacitance verses voltage and time dependent dielectric breakdown measurements. We also looked for Si substrate damage in these samples using deep level transient spectroscopy and Schottky barrier current-voltage measurements. This characterization showed oxide damage varied widely with ashing tool. In all cases, however, there was no significant Si substrate damage.

Conductive SrVO3-x films are deposited directly on Si(100) substrates by vacuum evaporation method using SrVO3-x as a source material. It has been found that the conductive film was strongly oriented to only <100> direction on Si(100). By introducing hydrogen, the resistivity of the SrVO3-x film decreases to 0.57mΩcm, which is smaller than those of samples deposited without hydrogen.

Preferred crystallographic orientation has long been recognized to play an important role in interconnect reliability where a strong (111) texture improves electromigration lifetime. Detailed microstructural analyses have enabled the role of texture to be better understood. Although Bragg-Brentano scans are often used to characterize texture, it is shown that this technique gives incomplete and sometimes misleading information. The pole figure technique provides a complete description of the texture. The measurement and presentation of textures consider experimental aspects unique to thin film analysis as a prerequisite to developing quality data. Five textural archetypes are identified, and metrics presented for their quantification. Processing effects on texture are complex and depend on all facets of deposition conditions, on substrate/underlayers, and on annealing. General trends and specific examples of the impact of each aspect are given where it will be shown that deposition conditions and the presence of underlayers have the greatest influence. The role of texture on reliability is considered for four failure modes: thermal hillocks, grain collapse, stress voiding, and electromigration. Electromigration results are emphasized where texture must be considered in the context of grain structure, in general, and, more specifically, the ratio of line width to grain size. Most measures of microstructure and reliability are statistical. The importance of local microstructural analysis will be emphasized in terms of both the arrangement of grains relative to the line dimension and microtexture characterization of the grain-to-grain misorientations.

Increasing circuit densities produce higher metal wiring aspect ratios, and more difficult feature fill for damascene processing. One method of extending the use of sputter deposition to challenging aspect ratios is to collimate the sputtered flux using a collimator plate, and to avoid randomizing the collimated flux by using low process pressures corresponding to long sputtered atom mean free paths. In this paper, we discuss our fabrication of damascene AI-0.5Cu-2Si and AI-2Mg wiring using both collimated and uncollimated sputtering, and our observations of collimation-induced changes in Al alloy electromigration and microstructure. Our experiments show that collimation has only a small effect on AlCuSi, but a large effect on AIMg. Specifically, the median time to electromigration failure for collimated AIMg was ∼10X the value for uncollimated AlMg and ∼6X the values for collimated and uncollimated AlCuSi. Transmission electron microscope and x-ray diffraction analyses of these films show that the collimation-induced improvement in AIMg t50 is associated with the formation of smaller, lower strain grains which are clustered in very well-oriented (111) domains. We propose that the advantageous AlMg microstructure results from enhanced texture produced by aspects of the collimated deposition active in the absence of incoherent precipitates.

A strong correlation has been established between TiN substrate anneal ambient and electromigration performance of Al-based alloys. Excellent electromigration lifetimes were measured for AlSiCu (and AlCu) films on sputtered TiN substrates annealed in N2 and slowly cooled down in furnace. The films annealed in N2-O2 and N2-H2 showed poorer electromigration performance, in that order. Stronger Al (111) texture, larger median grain size and uniform grain size distribution have been responsible for the improved electromigration performance of the N2-annealed (furnace-cooled) films. On the contrary, Al alloy films on TiN substrates annealed in N2 (but air-cooled), N2-O2, or N2-H2 ambient showed weaker Al (111) textures and smaller median grain sizes.

The various equations used by different authors for describing electromigration are compiled. All of them can be derived from a general equation which is based on a vacancy model. During the derivation of simplified versions of the general equations assumptions have to be made and their effect on concentration profiles and/or electromigration stresses developing as a function of time are discussed. Consequences with respect to Blech's experiment or the current exponent in Black's equation are taken into consideration and a simple explanation is provided for the beneficial effect of a (111) texture on the reliability of Al-lines.

Both electromigration lifetime experiments and experiments of the drift velocity type have been conducted with the alloys: Al(2% Cu), Al(O.5% Cu,O.3% Zr), and Al(0.3% Pd,O.3% Nb) also with structures with two wiring levels of Ti/Al(0.5 - 4 % Cu)/Ti interconnected with W studs. The latter structure and these structures in general, are representative of present applications, which contain Al alloy/W interfaces. In all cases it was found that the mass transport along the line's edges played a role in their damage formation, which was at least as great as grain boundary diffusion. It is postulated that the results obtained using the traditional test structure, which has reservoirs of metal alloy at each electrode and is conducted at a single level, have been misinterpreted as indicating that flux divergence at triple junctions were critical failure sites for on-chip interconnections. These present results show that the material in the electrode pads of the conventional structure can resupply material to the lines. A direct experimental comparison of the two structural types is made to demonstrate the point.

Thermal stresses may affect significantly electromigration induced open failures in nearbamboo interconnect structures ending in W-vias. Based on a physical model, we investigate the thermal stress effects on void nucleation, on early failures due to grain boundary diffusion, and on longer term bulk diffusion dominated failures. It is shown that thermal stress is all important as far as early failures are concerned. In particular, during accelerated tests and service, the early failures, when occur, arise due to stress and current directed grain boundary diffusion along grain clusters. In the accelerated test, bulk diffusion dominated void growth at vias determines the long term failures while during service bulk diffusion contribution is usually negligibly small within time frames of practical interest. Because the dominant failure mechanisms change, the extrapolation from the accelerated tests to the service conditions is not straight-forward.

Microstructural studies of electromigration failure were performed on A1-2Cu-1Si interconnects with 1.3 μm width. The lines were tested to failure under controlled conditions after pre-aging for various times at three different temperatures. Examination of the microstructure of the failure sites suggests that the lines fail at the bamboo grains that terminate the longest polygranular segments in the line. Transgranular slit voids form after Cu has been swept from the grain that fails. Hence, pre-aging lines to create a more stable distribution of Cu lengthens the time required to sweep Cu and significantly increases the time to failure. The optimal microstructure has a maximum intragranular density of stable θ precipitates. In this case transgranular slit failure is suppressed, and the bamboo grain fails by diffuse thinning to rupture.

Grain-bondary erosion-type voids and transgranular slit-like voids are found to be two competing electromigration failure modes in VLSI interconnects. The effects of interconnect linewidth, microstructure, process variables and stress conditions on the two failure modes were studied.

Several phenomena related to the short-length effect were observed during lifetime measurements of a two-level structure consisting of Ti-AICu-Ti stripes connected by interlevel tungsten (W) stud-vias. A linear increase in resistance was followed by a resistance change with time that approached zero. The threshold product is not a constant at 250 °C for stripe lengths of 30, 50 and 100 μm. The sigma of the lognormal distribution increased as the current density decreased and/or as the fail criterion increased. The lifetime, or t50, at relatively small current densities did not obey Black's empirical equation. Rather, the lifetime data obeyed a modified version of this equation that includes a critical current density, jc, as a new parameter. This critical current density is strongly dependent on the fail criterion, but is independent of temperature in the range 210-250 °C.

In this paper, the effect of thin film deposition conditions on the multilayer interconnect reliability was studied. Experimental results indicated the most reliable TiN/AICu/TiN interconnect was obtained at the deposition temperature of 350 °C without any substrate bias. This observation was in close agreement with thin film characteristics such as resistivity, grain size and intermetallic formation seen for those deposition conditions. SEM pictures showed the anti-reflective coating (ARC) TiN film did successfully suppress inter-plane extrusion during electromigration test. The failure mechanism for electromigration was also revealed to be mass transport as the result of the grain boundary diffusion instead of catastrophic open failures. The stress migration studies found that TiN/AICu/TiN had superior stress migration resistance than AICu alone.