For the 70nm CMOS node, it is anticipated that conventional implantation and spike annealing approaches, even with pre-amorphisation and co-implantation, are unlikely to provide pMOS junctions consistent with the ITRS requirements. Here the junction performance is limited by equilibrium solid solubility.

As laser annealing and in-situ doping techniques currently have unsolved integration problems, there is a renewed interest in using solid phase epitaxial regrowth (SPER) to form ultra-shallow metastable junctions. Such junctions have the potential to have an active dopant profile similar to the as-implanted profile. This offers above equilibrium solid solubility and abrupt profiles compatible with 70nm and even 45nm nodes. However there are concerns about residual defects, deactivation, diffusion and uniformity.

In this paper we show how the Ge, F and B implant and SPER anneal can be optimised for abrupt, uniform and highly activated B junctions. There is latitude for higher doses and energies than conventional implants, however results show that this may lead to clustering causing enhanced deactivation and reduced mobility. We give attention to the probing issues involved in characterising partially annealed junctions.

With this approach, p-type junctions having a sheet resistance of 265 ohms/sq and depth of 22nm are realised which are compatible with 70nm and potentially 45nm CMOS nodes.

The interactions between self-interstitials (I's) produced by 20 keV silicon implantation, and substitutional carbon in silicon have been studied using a Si1-yCy layer interposed between a near surface I source and a deeper B spike used as a marker for the I concentration. The Si1-yCy layer behaves as a filtering membrane for the interstitials flowing towards the bulk. This trapping ability is related to the total C amount in the Si1-yCy membrane. Substitutional carbon atoms interacting with self-interstitials are shown to trap I's, to be removed from their substitutional sites, and to precipitate into the C-rich region. After precipitation, C atoms are not able to further trap injected self-interstitials. The atomistic mechanism leading to Si-interstitial trapping has been investigated by developing a simulation code describing the migration of injected interstitials. By a comparison with the experimental data it was possible to derive quantitative indications on the trapping mechanism. It is shown that one Si-interstitial is able to deactivate about two C traps by means of interstitial trapping and C-clustering reactions.

Continued device scaling requires the formation of ever-shallower junctions with low resistance. A desirable option to form these junctions is still the use of conventional ion implantation. However in order to meet the junction depth/sheet resistance goals, a strong reduction in implant energy and increase in implant dose is required. Earlier work for B and BF2-implants, has suggested that during low energy ion implantation self-sputtering may become an important factor influencing/limiting the retained dose. The basic mechanism for the selfsputtering with increasing dose is the increasing dopant concentration at the surface leading to an increased probability for re-emission by the sputtering process. Simple models describing ion retention in combination with sputtering are based on this concept and indeed predict a selfsputtering process limiting the final retained dose. Unfortunately the theoretical calculations only predict a significant sputtering at doses >51016 at/cm2 whereas experimental results already show a limit in retained dose at 5 1015at/cm2.

In order to confirm the experimental data, low energy B, BF2, As and Sb implants have been made. Dose retention was monitored using nuclear reaction analysis and RBS whereby details of the dopant profile (redistribution) were studied using high resolution SIMS. For As and Sb no self-sputtering up to a dose of 1 1016at/cm2 can be found. For B a small dose loss (<10%) is seen significantly below the literature data. For BF2 a 20 % dose loss is observed. None of the SIMS profiles provide sufficient evidence for enhanced B-surface migration as required to explain the enhanced self-sputtering. On the other hand such a surface migration is reminiscent of the observations in SIMS whereby also an enhanced mobility of B during ion irradiation is required to explain the anomalous B-surface peak in many SIMS profiles. Based on the SIMS profiles a component sputter yield for B can be derived which is significantly higher than the matrix sputter yield suggesting a weak bonding of the segregated species leading to a reduced surface binding energy and thus enhanced sputtering yield.

In this work a rate equations model describing the interstitials (I) diffusion in a trap containing medium is presented. The model takes into account the interstitial injection by implantation and annealing and the surface evaporation. We found an analytical approximated solution of the model which allows clarifying the interplay between the parameters involved and a simple comparison with experimental data obtained by the analysis of boron delta doping arrays broadening. The calculations allow to demonstrate that the I injected into the bulk and toward the surface at the end of the I clusters dissolution does not depend on the detailed time evolution of the I clusters, but only on the total amount of I produced by the implantation. The fitting of the experimental data allows to easily quantifying important physical parameters such as the I evaporation rate at the surface and the density of intrinsic interstitial traps. Applications of the model are shown in the case of MBE materials intentionally doped with substitutional C. The model successfully predicts the TED reduction by MBE intrinsic I-traps and allows to estimate the average composition of Interstitial-Carbon clusters.

The influence of low temperature pre-annealing on p+/n ultra-shallow junction was investigated. An ultra-shallow junction was formed by means of B2H6 plasma doping at an energy of 500V. The activation was performed by excimer laser annealing. To study the low temperature annealing prior to laser annealing, furnace annealing at 300°C∼500°C for 5min was performed. Compared with control samples with no pre-annealing, the low temperature preannealing significantly improves junction characteristics, resulting in a reduction of junction depth and a lower leakage current density. A cross-sectional transmission electron microscopy analysis confirmed the lower defect density, which explains the lower leakage current. By optimizing the process conditions, excellent electrical characteristics of the p+/n ultra-shallow junction such as a junction depth of 28nm and a sheet resistance of 250Δ/sq. can be obtained.

Low temperature shallow junction formation is an attractive activation technique for 70nm technology node and beyond as it can easily be integrated into device structures that are formed using disposable spacer (reverse source drain extension formation) or low power CMOS devices using high-k/metal gate stack structures. Therefore, this paper will first review the shallow junction requirements as stated in the 2001 ITRS (international technology roadmap for semiconductors) and it's interpretation to ion implantation shallow junction formation for various dopant activation and annealing techniques. First high temperature (>1000°C) RTA spike, flash or sub-melt laser annealing techniques with oxide or oxynitride/polysilicon electrode gate stack structures will be discussed and its limitations to >8E19/cm3 boron electrically active dopant level due to boron solid solubility limit in silicon satisfying only the 100nm technology node requirement (2003). Next, higher temperature laser melt annealing (1200°C to 1400°C) will be discussed and it's applicability beyond 70nm node technology (2006) to 25nm node (2016) where boron solid solubility limit is up to 5E20/cm3. However, if high-k (HfO) dielectric/metal electrode gate stack structures are to be used starting at sub-100nm node in 2005 for low power CMOS then low temperature (>700°C) annealing must be used for shallow junction formation to prevent recrystallization and dielectric constant degradation. Using low temperature SPE (solid phase epitaxial regrowth) annealing techniques in the 550°C to 750°C for short anneal times of >5mins., shallow & abrupt junctions 8.0nm deep, >2.0nm/decade with up to 2.5E20/cm3 boron electrical active dopant level can be achieved satisfying the 25nm technology node (2016) requirements.

Molecular beam epitaxial Si1-xGex layers of various Ge concentrations ranging from 0% to 50% were grown on top of a Si substrate. The wafers were then implanted with a 40 keV, 1 x 1014cm-2 Si+. To study the development of {311} defects, the samples were annealed at 750°C for times ranging from 0 to 20 minutes. TEM was utilized to observe both the formation and dissolution of the defects. The Si1-xGex samples with ≤ 5% Ge exhibit {311} defect formation and dissolution; however, samples with the Ge content lying between 15% and 50% showed only dislocation loop formation. It is suggested that the decrease in bond strength with increasing Ge content is the reason for the lack of {311} defect formation.

We present an extensive study of the thermal evolution of the extended defects found in ion implanted Si as a function of annealing conditions. We will first review their structure and energetics and show that the defect kinetics can be described by an Ostwald ripening process whereby the defects exchange Si atoms and evolve in size and type to minimise their formation energy. Finally, we will present a physically based model to predict the evolution of extrinsic defects during annealing through the calculation of defect densities, size distributions, number of clustered interstitials and free-interstitial supersaturation. We will show some successful applications of our model to a variety of experimental conditions and give an example of its predictive capabilities at ultra low implantation energies.

Silicon-on-insulator (SOI) is a promising alternative to bulk silicon as ultra shallow junction depths have begun to shrink below 50 nm. This study examined the effect of the SOI surface silicon/buried oxide interface on {311} defect evolution after Si+ ion implantation. SOI wafers were produced such that the surface silicon thickness varied from 300Å to 1600Å. Non-amorphizing Si+ implants at 5 and 20 keV with a dose of 2x1014 cm-2 were performed into SOITEC SOI wafers. Furnace anneals were done at 750°C from 5 minutes to 4 hours and quantitative transmission electron microscopy (QTEM) was used to study the implant damage evolution. At 5 keV, the dissolution behavior of the SOI was very similar to that of the bulk. However, the extended defects in the 300 Å SOI did not nucleate the same as those observed in the bulk or thicker SOI. Similar results were seen at 20 keV for the 700 Å SOI, but a slight decrease in the concentration of trapped interstitials was observed due to interface recombination as a result of the increased projected range of the implant. It is concluded that the surface Si/BOX interface does not significantly affect recombination of interstitials trapped in extended defects unless the interstitial profile is close to or truncates the interface. However, the interface does appear to affect the stability of zig-zag {311} defects and dislocation loops in thin SOI at lower implant energies.

Growth conditions for epitaxy of Si1-x-yGexCx and Si1-xCx alloy layers on (100) silicon substrates by rapid thermal chemical vapor deposition (RTCVD) with disilane as the silicon source gas are described and the Si1-xCx conditions are compared to previously reported RTCVD growth conditions for epitaxy of Si1-xCx using silane as the source gas. The thermal stability of the layers at 850°C in nitrogen is examined using x-ray diffraction as a measure of the average substitutional carbon concentration in the layers after annealing. A characteristic time constant to describe the reduction of average substitutional carbon concentration in the layer is extracted from the XRD measurements. The characteristic time constants are found to agree within a factor of 3 with that observed in previous reports. However, the time constants are found to depend more strongly on the as-grown substitutional carbon concentration than what is predicted by simple precipitation kinetics, assuming carbon diffusion to a constant number of nucleation centers.

New, non-routine metrology issues are addressed for three kinds of materials and processes that are necessary for the fabrication of ultra-high speed devices. We look at the problems and solutions for measuring both stoichiometry and dopant content of SiGe material when using Cs primary ion bombardment. We examine the challenges of determining the N content of ultra-thin SiON gate dielectrics with emphasis on what will be necessary for the measurement of 1nm thick oxides. And finally we show some promising early results of using a new protocol for measuring ULE B ion implant profiles in the top 3nm with emphasis on obtaining a more realist profile shape in this region for TCAD modeling purposes.

In this work, we report data for the growth kinetics of locally confined dislocation loops organized within lines of controlled dimension and periodicity. The dislocation loop lines were formed in the crystalline substrate after local Si implantation and annealing in predefined areas. The distance between the lines ranges between 0.2 νm to 5 μm. It is shown that the kinetics of the DLs depends on the distance between them. When the distance is less than 1 μm, the DLs behave in a similar fashion like those grown in a continuous layer, under inert and oxidizing conditions. However, when the distance between the lines is increased (eg. 5 μm), the behavior of the loops is changed. Fast dissolution of the dislocations loops is observed during annealing in inert ambient, due to enhanced interstitial losses, while under oxidizing conditions the loops grow faster.

Laser Thermal Processing (LTP) involves laser melting of an implantation induced preamorphized layer to form highly doped ultra shallow junctions in silicon. In theory, a large number of interstitials remain in the end of range (EOR) just below the laser-formed junction. There is also the possibility of quenching in point defects during the liquid phase epitaxial regrowth of the melt region. Since post processing anneals are inevitable, it is necessary to understand both the behavior of these interstitials and the nature of point defects in the recrystallized-melt region since they can directly affect deactivation and enhanced diffusion. In this study, an amorphizing 15 keV 1 x 1015/cm2 Si+ implant was done followed by a 1 keV 1 x 1014/cm2 B+ implant. The surface was then laser melted at energy densities between 0.74 and 0.9 J/cm2 using a 308 nm excimer-laser. It was found that laser energy densities above 0.81 J/cm2 melted past the amorphous-crystalline interface. Post-LTP furnace anneals were performed at 750°C for 2 and 4 hours. Transmission electron microscopy was used to analyze the defect formation after LTP and following furnace anneals. Secondary ion mass spectrometry measured the initial and final boron profiles. It was observed that increasing the laser energy density led to increased dislocation loop formation and increased diffusion after the furnace anneal. A maximum loop density and diffusion was observed at the end of the process window, suggesting a correlation between the crystallization defects and the interstitial evolution.

Future CMOS technology nodes bring new challenges to formation of source/drain junctions and their contacts. To avoid MOSFET performance degradation with scaling, series resistance contribution of each junction must be limited to five percent of the device channel resistance. This requires ultra-shallow junctions with extremely low sheet, spreading and contact resistance. In this paper, we present an overview of the SiGe junction technology recently proposed by this laboratory for nanoscale CMOS. The technology is based on selective deposition of boron or phosphorus doped SiGe alloys in source/drain regions isotropically etched to the desired junction depth. Since the dopant atoms naturally occupy the substitutional sites during growth, the need for an activation anneal is completely eliminated limiting the maximum process temperature to 550°C for boron and 750°C for phosphorus. In this temperature range, dopant diffusion is virtually eliminated resulting in extremely abrupt doping profiles. Elimination of the high temperature implant anneal also makes the process compatible with the thermal stability needs of future high-K gate dielectrics. A key advantage of the technology is its potential to reduce the junction contact resistance. SiGe provides a smaller bandgap under the metal contact resulting in a smaller metal-semiconductor barrier height. Since the contact resistivity is an exponential function of the barrier height, the technology provides a significant advantage in reducing the contact resistivity. The results to date indicate that the technology is a promising alternative for nanoscale CMOS source/drain junctions and their contacts.

One alternative to conventional rapid thermal annealing (RTA) of implants for ultra-shallow junction formation is that of laser annealing. Laser thermal processing (LTP) incorporates an excimer pulsed laser capable of melting the near surface region of the silicon (Si) substrate. The melt depth is dependent upon the energy density supplied by the irradiation source and the melting temperature of the substrate surface. A process window associated with this technique is able to produce similar junction depths over a range of energy densities due to the melting temperature depression established with pre-amorphization of the substrate surface prior to dopant incorporation. The process window of germanium (Ge) preamorphized, boron (B) doped Si was investigated. 200 mm (100) n-type Si wafers were preamorphized via 18 keV Ge+ implantation to 1x1015/cm2 and subsequently implanted with 1 keV B+ to doses of 1x1015/cm2, 3x1015/cm2, 6x1015/cm2, and 9x1015/cm2. The wafers were laser annealed from 0.50 J/cm2 to 0.88 J/cm2 using a 308 nm XeCl excimer irradiation source. Transmission electron microscopy (TEM) was used to determine the process window for each implant condition, and correlations between process window translation and impurity concentration were made. Four-point probe quantified dopant activation and subsequent deactivation upon post-LTP furnace annealing.

In summary, we find it is possible to model the extent of arsenic diffusion during front-end and back-end processes that define the final junction depth. The key features of the model can be summarised as: (a) Interstitials from implant damage play a diminished role as implant energies are scaled; (b) As4V formation and precipitation at high concentrations is critical to accurate modeling of ultra-shallow arsenic junctions. These models when used with device simulations help optimize transistor performance/tradeoffs.

We would like to thank Pavel Fastenko and Scott T. Dunham (University of Washington) for details and discussion regarding their modeling results.

Electromagnetic heating provides a novel alternative to “illumination-based” rapid thermal processing techniques. Exposure to radiation, in the RF and microwave frequency regimes, rapidly heats silicon (∼125°C/sec) to temperatures in excess of 1000°C without the use of a susceptor. These ramp rates make this technology suitable for the activation of shallow implanted dopants, and satisfaction of the 100 nm technology node has been achieved. Furthermore, the presence of high frequency electric fields creates ponderomotive forces that may alter the kinetics of dopant activation and diffusion. These additional driving forces could, once fully understood, lead to an enhanced activation mechanism that activates sufficient dopants to satisfy the 70 nm technology node at temperatures less than 1000°C.

A method for completely suppressing the transient enhanced diffusion (TED) of boron implanted in preamorphized silicon is demonstrated. Boron is implanted in a molecular beam epitaxy (MBE) grown silicon sample that has been previously amorphized by silicon implantation. The sample is then annealed in order to epitaxially regrow the amorphous layer and electrically activate the dopant. The back-flow of silicon interstitials released by the preamorphization end-of-range (EOR) damage is completely trapped by a carbon-rich silicon layer interposed by MBE between the damage and the implanted boron. No appreciable TED is observed in the samples up to complete dissolution of the EOR damage, and complete electrical activation is obtained. The method might be considered for the realization of ultra shallow junctions for the far future complementary metal-oxide semiconductor technology nodes.

A loop nucleation and evolution model in Si+ implanted Silicon was previously introduced [1]. In this study, the model is extended to predict end of range (EOR) and projected range defect nucleation and evolution created by different ion implant species such as Germanium, Arsenic and Boron. The model assumes that all the nucleated loops come from {311} unfaulting and the loop density and average loop radius follow a log normal distribution. The model is verified with the experimental data obtained from literature for Germanium [2], Arsenic [3] and Boron [4] implanted Silicon for different implant doses and energies. Modeling results are in agreement with the experimental results.

Medium energy ion scattering (MEIS), operated at sub-nm depth resolution in the double alignment configuration, has been used to examine implant and damage depth profiles formed in Si(100) substrates irradiated with 2.5 keV As+ and 1 keV B+ ions. Samples were implanted at temperatures varying between 150°C, and 300°C to doses ranging from 3X1014 to 2X1016 cm-2. For the As implants the MEIS studies demonstrate the occurrence of effects such as a dopant accommodation linked to the growth in depth of the damage layer, dopant clustering, as well as damage and dopant movement upon annealing. Following epitaxial regrowth at 600°C, approximately half of the As was observed to be in substitutional sites, consistent with the reported formation of AsnV complexes (n≤4), while the remainder became segregated and became trapped within a narrow, 1.1 nm wide layer at the Si/oxide interface

MEIS measurements of the B implants indicate the formation of two distinct damage regions each with a different dependence on implant dose, the importance of dynamic annealing for implants at room temperature and above, and a competing point defect trapping effect at the Si/oxide interface. B+ implantation at low temperature resulted in the formation of an amorphous layer due to the drastic reduction of dynamic annealing processes.

Notably different dopant distributions were measured by SIMS in the samples implanted with As at different temperatures following rapid thermal annealing (RTA) up to 1100°C in an oxidising environment. Implant temperature dependent interactions between defects and dopants are reflected in the transient enhanced diffusion (TED) behaviour of As.