The biaxial stress in Co thin-films has been investigated in situ by measuring changes in substrate curvature that occurred during deposition and annealing.Films of Co, 35 to 500 nm in thickness, were deposited by UHV magnetron sputtering at room temperature on Si (100) and poly-Si substrates.Results show that during Co deposition the bending force increased linearly with film thickness; a signature of constant stress.In addition, the stress evolution during silicide formation was measured under constant heating rate conditions from room temperature up to 700°C. The stress-temperature curve was correlated with Co2Si, CoSi, and CoSi2 phase formation using in situ synchrotron X-ray diffraction measurements.The room temperature stress for the CoSi2 phase was found to be ∼0.8 GPa (tensile) in the films deposited on Si (100) and ∼1 GPa (tensile) on the films deposited on poly-Si.The higher tensile stress in the poly-Si sample could be a result of Si grain growth during annealing.

We have clarified a new leakage mechanism in Co salicide process for the ultra-shallow junctions of 0.1-um CMOS devices and revealed the optimum Co salicide process conditions for minimizing the leakage current. We found that leakage currents generate from many localized points that are randomly distributed in the junction area, and not from the junction edge. We successfully verified our localized leakage model using Monte Carlo simulation. We identified abnormal CoSix spiking growth under the Co silicide film, as being the origin of the localized leakage current. These CoSix spikes grow rapidly only during annealing between 400°C and 450°C when Co2Si phase is formed. These spikes never grow during annealing at over 500°C, and decrease with high temperature annealing over 500°C. A minimum leakage current can be achieved by optimized annealing at between 800°C and 850°C for 30 sec. This is because a trade-off between reducing the CoSix spikes and preventing the Co atom diffusion from Co silicide film to Si substrate, which begins at annealing above 900°C.

We have studied CoSi2 formation in the presence of a Cr or Mo interlayer or capping layer. We shall show that, contrary to what was previously reported, Cr and Mo may be used as interlayers to grow epitaxial CoSi2. However, unlike for Ti, the thickness of the interlayer is very important. If the Cr or Mo interlayer is too thick (> 5 nm), polycrystalline CrSi2 or MoSi2 are formed first and epitaxial growth of CoSi2 becomes impossible. However, both XRD and random/channeling RBS results indicate that for a 2-3 nm interlayer of Cr or Mo, CoSi2 forms epitaxially on Si(100). For thinner interlayers, there is a preferential (220) and (400) orientation. This can be explained by the presence of Cr or Mo on the CoSi grain boundaries, which will affect the heterogeneous nucleation of CoSi2.

Uniform epitaxial CoSi2 layers have been grown in situ on a (100) Si substrate at temperatures near 600 °C by reactive chemical-vapor deposition of cyclopentadienyl dicarbonyl cobalt, Co(η5-C5H5)(CO)2. The growth kinetics of an epitaxial CoSi2 layer on a Si (100) substrate was investigated at temperatures ranging from 575 to 650 °C. In initial deposition stage, platelike discrete CoSi2 spikes were nucleated along the <111> directions in (100) Si substrate with a twinned structure. The discrete CoSi2 plates with both {111} and (100) planes grew into an epitaxial layer with a flat interface on (100) Si. For epitaxial CoSi2 growth on (100) Si, the activation energy of the parabolic growth was found to be 2.80 eV. The growth rate seems to be controlled by the diffusion of Co through the CoSi2 layer.

Electrical performance of in-situ steam generated (ISSG) oxide nitrided using remote plasma nitridation (RPN) has been evaluated. An equivalent oxide thickness (EOT) of 1.6 nm with gate leakage current around 5×10−3 A/cm2 (at −1.5V) has been achieved. The leakage current of remote plasma nitrided ISSG oxide is lower than that of ISSG only, where more than one order of magnitude leakage current reduction (at the same EOT) has been achieved for some RPN conditions. Moreover, it is observed that the extent to which the RPN process conditions modify device parameters such as EOT, flatband voltage (VFB), and time-to-breakdown (tbd) increases with decreasing ISSG thickness. The thinner ISSG oxides appear to be more susceptible to plasma damage and accumulation of positively charged nitrogen atoms at the oxide/Si interface. Therefore, RPN processes that use lower temperature and shorter time are preferred for very thin oxides. The nitrogen content and profile in the samples evaluated using SIMS analysis, indicate that RPN offers higher nitrogen content and better nitrogen profile compared to conventional nitrogen incorporation methods such as NO annealing [1].

A highly selective nitride etch was developed for gate stack spacer process in advanced memory programs. Based on methyl fluoride chemistry with better than 8:1 selectivity of nitride:oxide, this process exhibits minimal erosion to the underlying RTO thermal oxide for consistent diffusion ion-implant control. As the groundrule changed to 0.175um and below, a two-step etch scheme was employed to maintain the profile control in high-aspect-ratio structures. The stability and repeatability of the process is demonstrated in the SPC chart of the post etch FTA site measurement.

Stress-strain effects and physical processes during formation of the self-aligned silicides are analyzed. A new model for predictive simulation of the self-aligned silicidation is suggested. The model is based on suppression of diffusion and reaction rate of the silicon atoms inside silicide in the presence of oxygen atoms, injected into silicide from the neighbor oxide regions such as oxide spacer, TEOS at STI (Shallow Trench Isolation) and pad oxide. The model is demonstrated to explain the experimentally observed silicide shape.

Poly Si1−xGex films have been suggested as a promising alternative to the currently employed poly-Si gate electrode for CMOS technology due to lower resistivity, less boron penetration, and less gate depletion effect than those of poly Si gates. We investigated the formation of poly Si1−xGex films grown by UHV CVD using Si2H6 and GeH4 gases, and studied their microstructures as well as their electrical characteristics. The Ge content of the Si1−xGex films increased linearly with the flux of the GeH4 gas up to x=0.3, and saturated above x=0.45. The deposition rate of the poly Si1−xGex films increased linearly with the flux of the GeH4 gas up to x=0.1, above which it is slightly changed. The resistivity of the Si1−xGex films decreased as the Ge content increased, and was about one half of that of poly-Si films at the Ge content of 45%. The C-V measurements of the MOSCAP structures with poly Si1−xGex gates demonstrated that the flat band voltage of the poly Si1−xGex films was lower than that of poly-Si films by 0.2V.

The formation of a uniform, low-resistance silicide is dependent on the contamination level of the silicon surface upon which the Ti or Co is deposited. Contamination may be in the form of embedded carbon and fluorine residues from previous processing steps, such as the LDD spacer etch. The extent to which the spacer etch contributes impurities can be determined by making contact angle measurements; that is, measurement of the angle formed by a droplet of water placed on the wafer surface. A clean silicon surface provides a contact angle of > 70°, whereas a contaminated silicon surface produces contact angles down to only a few degrees. By using contact angle as a metric, a post-spacer etch clean was developed to remove impurities from the silicon surface without significant silicon loss. The clean procedure entails the use of a CF4/H2O plasma to treat the wafer directly after spacer etch. The clean process was then evaluated by the formation of a blanket Ti silicide followed by sheet resistance measurement. By using this cleaning process, a Ti silicide sheet resistance comparable to that formed on virgin silicon wafers was obtained on wafers that experienced the spacer etch. By comparison, wafers that were subjected to the spacer etch but not the post-spacer clean yielded a higher sheet resistance. Additional study of the post-spacer etch clean process revealed that oxide on the wafer (even the small amount formed during an O2-based resist ash process) can prevent the CF4/H2O plasma from cleaning the surface, perhaps by blocking H in the cleaning plasma from extracting C and other contaminants from the silicon surface. Co silicide formation is even more sensitive to surface impurities than Ti silicide. Using the same post-spacer etch clean, uniform, low-resistance Co silicide formation has been demonstrated.

Titanium boride is known as a good diffusion barrier, in particular against copper, however outdiffusion of boron might deteriorate the semiconductor device. A TiSi2 sublayer prevents effectively boron penetration into the Si substrate. In this study the intention was to form a TiB2/TiSi2 bilayer film by silicidation of a titanium-rich titanium boride deposited by magnetron co-sputtering from elemental targets. The TiSi2 formation as well as the redistribution of titanium in the boride layer has been investigated by X-ray diffraction (XRD), Auger depth profiling and cross-sectional transmission electron microscopy (XTEM). Contact structure with Cu metallization was prepared to characterize this structure electrically.

The Ti-rich titanium boride film was completely amorphous by XRD up to 700 °C. Crystallization of Ti-rich silicides (Ti3Si, Ti5Si3) have started at 750 °C, but already at 800 °C crystallization of C54 TiSi2 was completed. TiB2 begins to crystallize at 800 °C. Sheet resistance measurements confirmed these results. The sheet resistance of the as-deposited film was about 16 ω/□ and no significant change was detected up to 700 °C. Then, a remarkable drop in the sheet resistance to ∼1 Ω/□ was obtained after 800 °C, and this value was actually unchanged up to 925 °C. Cross-sectional TEM revealed the formation of the C54 TiSi2 layer between TiB2 and Si and additionally, a second C54 TiSi2 layer was observed within the boride film. Current-voltage measurements of the prepared contact structure showed that it was a Schottky diode with very high leakage current.

In this paper, we report a process for the preparation of high quality amorphous tantalum oxynitride (TaOxNy) via ammonia annealing of Ta2O5 followed by wet reoxidation for use in gate dielectric applications. Compared with tantalum oxide(Ta2O5), a significant improvement in the dielectric constant was obtained by the ammonia treatment followed by light reoxidation in a wet ambient. We confirmed nitrogen incorporation in the tantalum oxynitride (TaOxNy) by Auger Electron Spectroscopy. By optimizing the nitridation and reoxidation process, we obtained an equivalent oxide thickness of less than 1.6nm and a leakage current of less than 10mA/cm2 at -1.5V. Compared with NH3 nitridation, nitridation of Ta2O5 in ND3 improve charge trapping and charge-to-breakdown characteristics of tantalum oxynitride.

Evidence is presented that the nucleation of CoSi2 can be influenced by the presence of small amounts of other elements. The presence of trace amounts of Ti in the CoSi (originating from either a Ti capping layer or interlayer) causes an increase in the CoSi2 nucleation temperature. Moreover, the presence of Ti in the CoSi induces a preferential orientation of the CoSi2 : for an increasing amount of Ti, we observed a transition from polycrystalline CoSi2 over preferential (220) orientation towards epitaxial (400) CoSi2. We observed similar effects for other elements (e.g. Ta, W, C, Mo, Cr). We were able to explain these findings based on the heterogeneous nucleation of CoSi2.