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Three-Dimensional Integration Technology for Advanced Focal Planes

Published online by Cambridge University Press:  01 February 2011

Craig Lewis Keast ,
Brian Aull ,
James Burns ,
Chenson Chen ,
Jeff Knecht ,
Brian Tyrrell ,
Keith Warner ,
Bruce Wheeler ,
Vyshi Suntharaligam  and
Peter Wyatt
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Craig Lewis Keast
Affiliation:
keast@ll.mit.edu, MIT Lincoln Laboratory, United States
Brian Aull
Affiliation:
aull@ll.mit.edu, MIT Lincoln Labroatory, Lexington, Massachusetts, United States
James Burns
Affiliation:
jab@ll.mit.edu, MIT Lincoln Labroatory, Lexington, Massachusetts, United States
Chenson Chen
Affiliation:
chen@ll.mit.edu, MIT Lincoln Labroatory, Lexington, Massachusetts, United States
Jeff Knecht
Affiliation:
jmk@ll.mit.edu, MIT Lincoln Labroatory, Lexington, Massachusetts, United States
Brian Tyrrell
Affiliation:
tyrrell@ll.mit.edu, MIT Lincoln Labroatory, Lexington, Massachusetts, United States
Keith Warner
Affiliation:
warner@ll.mit.edu, MIT Lincoln Labroatory, Lexington, Massachusetts, United States
Bruce Wheeler
Affiliation:
wheeler@ll.mit.edu, MIT Lincoln Labroatory, Lexington, Massachusetts, United States
Vyshi Suntharaligam
Affiliation:
vyshi@ll.mit.edu, MIT Lincoln Labroatory, Lexington, Massachusetts, United States
Peter Wyatt
Affiliation:
wyatt@ll.mit.edu, MIT Lincoln Labroatory, Lexington, Massachusetts, United States
Donna Yost
Affiliation:
yost@ll.mit.edu, MIT Lincoln Labroatory, Lexington, Massachusetts, United States
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Abstract

We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using it.

Keywords

CMPbondingsemiconducting
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1112: Symposium E – Materials and Technologies for 3-D Integration , 2008 , 1112-E01-02
Copyright
Copyright © Materials Research Society 2009

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References

REFERENCES

1) Burns, J.A., et al., “A Wafer-Scale 3-D Circuit Integration Technology”, IEEE Transactions on Electron Devices, vol. 53, no. 10, pp. 2507–2516, Oct. 2006.Google Scholar
2) Burns, J.A., et al., “Three-dimensional integrated circuits for low power, high bandwidth systems on a chip”, 2001 ISSCC Int. Solid-State Circuits Proceedings, Digest of Technical Papers vol. 44, pp. 268–269, Feb. 2001.Google Scholar
3) Suntharalingam, V., et al., “Megapixel CMOS Image Sensor Fabricated in Three-Dimensional Integrated Circuit Technology”, 2005 ISSCC Int. Solid-State Circuits Proceedings, Digest of Technical Papers vol. 48, pp. 356–357, Feb. 2005.Google Scholar
4) Aull, B., et al., “Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes with Two SOI Timing Circuit Layers”, 2006 ISSCC Int. Solid-State Circuits Proceedings, Digest of Technical Papers vol. 49, pp. 304–305, Feb. 2006.Google Scholar