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Study of Magnetron Sputter Deposition of Metal Gate Electrodes

Published online by Cambridge University Press:  01 February 2011

Mengqi Ye ,
Dave Liu ,
Peijun Ding ,
Steven Hung  and
Khaled Ahmed
Mengqi Ye
Affiliation:
mqye@yahoo.com, Applied Materials, Inc., Thin Films Group, 3050 Bowers Ave., M/S 1158, P.O. Box 58039, Santa Clara, CA, 95054, United States
Dave Liu
Affiliation:
dave_liu@amat.com, Applied Materials, Inc., 3050 Bowers Ave., P.O. Box 58039, Santa Clara, CA, 95054, United States
Peijun Ding
Affiliation:
peijun_ding@amat.com, Applied Materials, Inc., 3050 Bowers Ave., P.O. Box 58039, Santa Clara, CA, 95054, United States
Steven Hung
Affiliation:
steven_hung@amat.com, Applied Materials, Inc., 3050 Bowers Ave., P.O. Box 58039, Santa Clara, CA, 95054, United States
Khaled Ahmed
Affiliation:
khaled_ahmed@amat.com, Applied Materials, Inc., 3050 Bowers Ave., P.O. Box 58039, Santa Clara, CA, 95054, United States
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Abstract

A systematic study of magnetron sputter deposition of metal gate is presented. On-wafer probes were used to measure ion current and floating voltage. Charge monitoring wafers was used to evaluate charging damage. C-V measurements showed that the interface trap density of metal gated MOS capacitors was reduced with thicker dielectric layer thickness and with the insertion of ALD deposited buffer layer. Lower pressure, higher sputtering power, and pulsed DC sputtering were found to cause larger plasma damage to the ultra-thin dielectric layer, most likely due to increased energetic particle bombardment as a result of higher plasma density and higher ion and neutral energies.

Keywords

sputteringplasma depositionphysical vapor deposition (PVD)
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 917: Symposium E – Gate Stack Scaling – Materials Selection, Role of Interfaces, and Reliability Implications , 2006 , 0917-E12-05
Copyright
Copyright © Materials Research Society 2006

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